L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 179

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Packet_Buffer_Queue_Limit (Revision C Only)
Description: Global queue entry in buffer limit imposed when queue memory is congested.
Table 239. Packet_Buffer_Queue_Limit Register Parameters
Table 240. Packet_Buffer_Queue_Limit Field Parameters
This register defines the number of queue entries in packets that each queue is allowed to have during times of
queue memory congestion. If the queue memory is congested and the number of queue entries for any supervisor
queue exceeds the supervisor_queue_limit[12:0] or for any other queue exceeds the
queue_limit[12:0] value, then that queue is disabled from receiving further entries. If a queue is in excess of
its limit when the queue memory becomes congested, its excess queue entries are not discarded; only new entries
are inhibited from being enqueued.
This register is valid in revision C only, and the hol_mode bit in the packet_buffer_mode register must be asserted
to use this register.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
supervisor_queue_limit[12:0]
queue_limit[12:0]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Parameter
Field Name
2
3
4
supervisor_queue_limit[12:0]
5
Figure 172. Packet_Buffer_Queue_Limit Register Diagram
6
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
9
10
Agere Systems - Proprietary
11
Instances = 1
Instances = 1
Offset = 0.17
Mode = R/W
Mode = R/W
Parameters
0x000C_E204
Offset = 0.1
12
Value
13
NA
NA
4
1
4
1
14
15
16
17
Supervisor queue limit.
Queue limit.
18
19
20
21
queue_limit[12:0]
22
23
8
Description
24
7
25
6
26
5
27
4
28
3
29
2
ET4148-50
30
1
31
0
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