L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 292

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Preliminary Data Sheet
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
April 2006
Appendix B: Configuration
(continued)
Other Networking Functions
(continued)
Transmit Descriptors. Each entry in the transmit FIFOs is a pointer to a transmit descriptor. Each transmit
descriptor is a list of one or more 2-word (32-bit words) records that identify the various segments that make up a
transmit packet.
Each 2-word structure consists of a pointer to a transmit segment, a segment length value, and a pair of flag bits:
last and indicate.
The last flag is asserted if the current record is the last record of the packet descriptor. Once a record is encoun-
tered with its last flag asserted, packet descriptor processing is terminated and the last byte of the associate
transmit segment is considered to be the last byte of the packet.
The indicate flag is asserted if it is desired to have an interrupt generated at the completion of packet transfer.
This function is used to enable the supervisor to keep track of the transmission process. Interrupts enabled by this
flag occur when the corresponding segment has completed its transfer across the PCI bus from the supervisor’s
memory to the ET4148-50’s internal memory. This event may precede the actual transmission of the packet by a
significant amount of time. In fact, the successful transfer of the packet (and its accompanying interrupt to the
supervisor) is no assurance that the packet has been or ever will be transmitted. Certain events such as MAC flow
control or maximum collisions on a half-duplex link may significantly delay or even prevent transmission.
Refer to the Supervisor_Tx_Descriptor_{0..1} data structure description on page 50 for further information.
Transmit Packet Segments. The transmit segments are simply contiguous bytes that are to be gathered up by the
ET4148-50 as part of a transmit packet. The transmit packets must utilize a format that conforms to that shown for
the Supervisor_Tx_Packet data structure. See page 52 for more details.
Refer to the Supervisor_Tx_Packet_Segment_{0..1} data structure description on page 53 and for further informa-
tion.
Supervisor Packet Reception
Eight of the 408 queues within the ET4148-50 are dedicated to the supervisor for packet reception purposes.
These eight queues correspond to bits 50 through 57 of the 58-bit destination map that is computed as part of the
bridging process.
There is a one-to-one correlation between these eight internal queues and the eight receive FIFOs that are main-
tained by the ET4148-50 in the supervisor’s memory space across the PCI bus.
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