L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 137

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Appendix A: Registers
Mac_Mode_{0..4}
Table 168. Mac_Mode_{0..4} Field Parameters (continued)
Agere Systems Inc.
gmac_rx_en_{}{0..9}
gmac_flow_control_initiate_en_{}{0..9}
gmac_rx_pause_en_{}{0..9}
REFERENCE
PORT
XG1
60
Field Name
XG0
50
(continued)
SU1
49
SU0
48
(continued)
G47
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
47
G46
46
Figure 127. Port Numbering Scheme
G45
PORT NUMBERING SCHEME
45
Instances = 1
Instances = 1
Instances = 1
Offset = 0.29
Offset = 0.30
Offset = 0.31
Mode = R/W
Mode = R/W
Mode = R/W
Parameters
Agere Systems - Proprietary
G44
44
Enables the reception of Ethernet packets. When false,
only MAC control packets are received.
This bit enables the initiation of flow control actions on
the part of the Ethernet MAC in response to flow control
indications from packet_buffer. If this bit is deas-
serted, then the corresponding Ethernet MAC never
takes any flow control actions.
In revision C, when input_select_{}{0..9}[1:0]
= 0x2 and auto_negotiate_en_{}{0..9} = 1, this
field becomes the ASM_DIR (PS2) bit for 1000BASE-X
autonegotiation.
This bit must be asserted for the corresponding Ethernet
MAC to react to the reception of MAC flow control pack-
ets.
In revision C, when input_select_{}{0..9}[1:0] =
0x2 and auto_negotiate_en_{}{0..9} = 1, this
field becomes the PAUSE (PS1) bit for 1000BASE-X
autonegotiation.
G3
3
G2
2
G1
1
G0
0
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
Description
ET4148-50
137