L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 66

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Electrical Specifications
Timing Diagrams
SFP SerDes I/O Clock Input Specification
Table 40. SFP SerDes Reference Clock Specifications
XAUI SerDes I/O Clock Input Specification
Table 41. XAUI SerDes Reference Clock Specifications
66
Clock Frequency—SFP (REFCLK_3)
Frequency Stability
Duty Cycle
Rise Time and Fall Time (20%—80%)
Differential Amplitude
Single-ended Amplitude
Common-mode Level
PLL Bandwidth
Input Capacitance
Skew, REFCLK_3_(P,N)
Jitter (peak-to-peak)
Clock Frequency—XAUI (REFCLK_4)
Frequency Stability
Duty Cycle
Rise Time and Fall Time (20%—80%)
Differential Amplitude
Single-ended Amplitude
Common-mode Level
PLL Bandwidth
Input Capacitance
Skew, REFCLK_4_(P,N)
Jitter (peak-to-peak)
Parameter
Parameter
(continued)
(continued)
Symbol
Symbol
Agere Systems - Proprietary
t
VCM
t
VCM
V
V
V
V
R
R
—
—
—
—
CI
—
—
—
—
—
—
CI
—
—
OD
OD
, t
SE
, t
SE
F
F
V
V
–100
–100
Min
Min
600
300
–75
600
300
–75
40
SE/
40
SE/
—
—
—
—
—
—
—
—
2
2
156.25
125.0
Typ
Typ
50
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD_3 – V
VDD_4 – V
2 x VDD_3
2 x VDD_4
VDD_3
VDD_4
Max
Max
100
100
100
100
1.2
2.0
1.2
2.0
60
12
75
60
12
75
—
—
Preliminary Data Sheet
SE
SE
/2
/2
Agere Systems Inc.
April 2006
mVp-p
mVp-p
mVp-p
mVp-p
ps
ps
Unit
MHz
ppm
MHz
Unit
MHz
ppm
MHz
pF
pF
ns
ps
ns
ps
%
%
V
V
p-p
p-p