L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 63

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Electrical Specifications
10G—3.125 Gbits/s SerDes Specifications
Table 35. Clocking and Timing Specifications
* Does not include in-band reference-clock jitter, which must be added to this. In-band jitter is defined as jitter with spectral content within the
Table 36. Transmitter Eye Diagram Values
* Ul = 320 ps.
Transmitter Output Jitter in Half-Rate Mode:
3 dB closed-loop bandwidth of the PPL.
Deterministic
Random
Total*
Deterministic Jitter
Total Jitter
Symbol
X1
X2
A1
A2
Parameter
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
–A2
–A1
(continued)
A2
A1
Transmitter HDOUT P-N Pair
0
0
0
Figure 31. Transmitter Eye Diagram
Agere Systems - Proprietary
X1
X1
0.175
0.390
0.17
0.35
400
800
(continued)
TIME (UI)
TIME (UI)
X2
X2
1 – X2
1 – X2
1 – X1
1 – X1
Min
—
—
—
1
1
Typ
—
—
—
UIp-p
UIp-p
Unit
mVp
mVp
UIp
Ulp
*
Max
0.10
0.14
0.24
ET4148-50
Ulp-p
Unit
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