L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 131

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Layer_2_Vlan_Mask_Table
Description: Enables the limiting of destinations based on source VLAN.
Table 161. Layer_2_Vlan_Mask_Table Register Parameters
Table 162. Layer_2_Vlan_Mask_Table Field Parameters
The received packet’s 8-bit VLAN index is used to retrieve a port mask from this table. This mask is then used to
eliminate destinations from the packet’s destination port map.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
vlan_mask[57:0]
0
4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
REFERENCE
1
Parameter
Field Name
2
PORT
3
SU7
4
57
5
SU6
56
6
Figure 121. Layer_2_Vlan_Mask_Table Register Diagram
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
SU1
9
51
Figure 122. Port Numbering Scheme
10
SU0
0x000c_3800
50
Agere Systems - Proprietary
Instances = 1
Mode = R/W
Parameters
11
Offset = 0.6
XG1
Value
PORT NUMBERING SCHEME
2048
49
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
256
NA
12
1
8
8
XG0
13
48
vlan_mask[31:0]
14
G47
47
15
G46
46
16
vlan_mask[57:32]
The VLAN mask.
G45
17
45
18
G44
44
19
20
21
22
9
Description
G3
23
8
3
24
7
G2
2
25
6
G1
1
26
5
G0
27
4
0
28
3
ET4148-50
29
2
30
1
31
0
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