L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 161

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Packet_Buffer_Free_Buffer_Control
Description: Free buffer list initialization controls.
Table 209. Packet_Buffer_Free_Buffer_Control Register Parameters
Table 210. Packet_Buffer_Free_Buffer_Control Field Parameters
Free buffer list initialization controls.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
free_buffer_initialization_start
free_buffer_initialization_done
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
Field Name
Parameter
1
2
3
Figure 155. Packet_Buffer_Free_Buffer_Control Register Diagram
4
5
6
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
7
8
9
Agere Systems - Proprietary
Instances = 1
Instances = 1
10
Offset = 0.30
Offset = 0.31
Parameters
Mode = WO
Mode = RO
11
0x000c_bb70
12
Value
13
NA
NA
4
1
4
1
14
15
16
Writing a one to this bit starts the initialization pro-
cess for the free buffer list.
This bit indicates that the initialization of the free
buffer list is complete. This bit is deasserted during
the initialization process.
17
18
19
20
21
22
Description
23
8
24
7
25
6
26
5
27
4
28
3
ET4148-50
29
2
30
1
31
0
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