L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 49

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Data Structures
Supervisor_Rx_Packet
Table 10. Supervisor_Rx_Packet Field Parameters
This data structure is used to present received packets to the supervisor. Zero or more of these data structures are
arranged within a FIFO structure maintained within the supervisor’s memory. The first word of
Supervisor_Rx_Packet always immediately follows the last word of the previous instance.
The first word of this data structure is a pointer to the remainder of the data structure. Ordinarily, these structures
are arranged contiguously. If the space at the end of Supervisor_Rx_Fifo{0..7} is insufficient to accommo-
date a maximum length packet, then Supervisor_Rx_Packet.packet_start_ptr[31:2] is used to point to
the start of Supervisor_Rx_Fifo{0..7}.
If there is insufficient space to accommodate a maximum length packet anywhere in
Supervisor_Rx_Fifo{0..7}, then the FIFO is considered full even though a smaller packet may fit.
If Supervisor_Rx_Fifo{0..7} is empty, then Supervisor_Rx_Packet is placed at
Supervisor_Rx_Fifo_Ptr_{0..7}.wr_ptr[31:2].
packet_start_ptr[31:2]
truncated
parity_error
vlan_index[7:0]
priority[3:0]
rx_port[5:0]
packet_length[13:0]
packet_data
Field Name
(continued)
Offset = 0.30
Offset = 4.12
Offset = 4.18
Parameters
Mode = RO
Offset = 0.0
Mode = RO
Mode = RO
Offset = 4.0
Mode = RO
Offset = 4.0
Mode = RO
Offset = 4.8
Mode = RO
Mode = RO
Mode = RO
Offset = 8.0
(continued)
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Agere Systems - Proprietary
Points to the status word of the associated receive packet. Ordinarily,
packet_start_pointer[31:2] and {rx_port[5:0],
packet_length[13:0]} are adjacent. However, in order to maintain
integral packets, these two words may be nonadjacent near the end of
the physical extent of a supervisor’s receive FIFO.
This value is written by the ET4148-50 and read by the supervisor.
If a receive packet is truncated because its length exceeds that set in
Supervisor_Maximum_Packet_Length, then this bit is asserted.
This bit is asserted if an internal parity error is detected at any time dur-
ing the transfer of a packet from the ET4148-50 across the PCI bus to
the supervisor.
The VLAN index assigned to a packet during reception.
The priority value assigned to a packet during reception.
This value identifies the physical port via which the packet was received.
This value is written by the ET4148-50 and read by the supervisor.
The length of a received packet. packet_length[13:0] is limited by
Supervisor_Maximum_Packet_Length. If packet_length[13:0]
equals Supervisor_Maximum_Packet_Length, then the packet may
have been truncated during the transfer.
This value is written by the ET4148-50 and read by the supervisor.
The packet data. Packet data is arranged in a big-endian fashion. The
last 32-bit word may contain zero or more pad bytes.
This value is written by the ET4148-50 and read by the supervisor.
Description
ET4148-50
49