L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 65

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L-ET4148-50C-DB

Manufacturer Part Number
L-ET4148-50C-DB
Description
Manufacturer
LSI
Datasheet

Specifications of L-ET4148-50C-DB

Lead Free Status / RoHS Status
Supplier Unconfirmed
Preliminary Data Sheet
April 2006
Agere Systems Inc.
Electrical Specifications
Timing Diagrams
PCI (continued)
Table 39. 3.3 V PCI Clock ac Specification
Clock-to-signal Valid
Float-to-active Delay
Active-to-float Delay
Setup Time
Hold Time
Parameter
(continued)
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
TRISTATE
OUTPUT
OUTPUT
(continued)
DELAY
DELAY
Output
INPUT
CLK
Figure 34. PCI Timing Diagram
Agere Systems - Proprietary
Symbol
t
t
OFF
ON
t
t
SETUP
t
HOLD
t
t
OFF
VAL
ON
t
t
t
VAL
VAL
SETUP
Min
2
2
3
0
t
HOLD
Typ
Max
14
6
ET4148-50
Unit
ns
ns
ns
ns
ns
65

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