L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 296

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix B: Configuration
Other Device Functions
Supervisor Endian
The supervisor’s PCI bus can operate in either a big-endian or a little-endian fashion. This operating mode is set
via the big_endian bit in the Supervisor_Endian register. Clearing this bit to zero places the PCI bus in its nor-
mal operating mode: little endian. Setting the bit causes the PCI bus to operate in big-endian manner.
It is recommended that 0000_0000
8000_0000
Interrupts
On-chip events may result in indications to the supervisor. These indications may, in turn, result in a hardware
interrupt. This hierarchy of events, indications, and interrupts is presented via a series of registers, records, and
fields that control which events may become indications and, in turn, which indications may become interrupts.
Signals that indicate the occurrence of the various events must pass through a mask before being presented to an
indication status register that is readable by the supervisor. This mask uses two write-only registers to set and clear
the mask bits. This technique of manipulating mask bits is done to make it possible to turn on or off a single bit or a
subset of bits with an atomic operation that cannot be interrupted.
The unmasked indication bits are then passed through an interrupt mask. This mask is managed in much the same
manner as the indication masks. Those indications that pass through the interrupt masks are presented via the
interrupt status registers to the supervisor. Bits asserted in the interrupt status register are also ORed together to
form a hardware interrupt to the supervisor.
Packet Buffer Scrubbing
To guard against the possibility of a buffer within the packet buffer becoming lost from the free list and, hence, no
longer available for packet storage operations, the ET4148-50 includes a packet scrubbing mechanism. This
mechanism is activated by writing the buffer number of a presumed-missing buffer into the
missing_buffer[14:0] field of the Packet_Buffer_Scrub register. The ET4148-50 takes that buffer number
and determines if it exists on the free list or any of the transmit queues or descriptors. If the buffer cannot be found,
it is added to the free list as a new entry. During the searching operation, the scrubbing bit is asserted by the
ET4148-50 in the Packet_Buffer_Scrub register.
296
16
or 0000_0001
Ind_Mask_Clear (write only)
Int_Mask_Clear (write only)
Ind_Mask_Set (write only)
Int_Mask_Set (write only)
16
. Doing so guarantees that the big_endian bit is set as desired.
(continued)
16
Figure 300. Indications and Interrupts
or FFFF_FFFF
(continued)
Agere Systems - Proprietary
16
be written to this register and to not bother with
EVENT INDICATION SIGNALS
Ind_Status (read only)
Ind_Mask (read only)
Int_Status (read only)
Int_Mask (read only)
INTERRUPT SIGNAL
Preliminary Data Sheet
Agere Systems Inc.
April 2006