L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 119

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Layer_2_Learning_Port
Description: Identifies the port to be used for MAC source address learning.
Table 137. Layer_2_Learning_Port Register Parameters
Table 138. Layer_2_Learning_Port Field Parameters
When a packet is received whose MAC source address is not found in the address table or whose source port
listed in the address table does not match the logical port through which it was received, it is copied to the port
number specified here.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
learning_port[5:0]
REFERENCE
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
PORT
1
Parameter
Field Name
2
SU7
57
3
SU6
4
56
5
6
Figure 100. Layer_2_Learning_Port Register Diagram
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
SU1
51
9
Figure 101. Port Numbering Scheme
0x000c_4668
SU0
50
10
Agere Systems - Proprietary
Instances = 1
Value
Offset = 0.26
Mode = R/W
Parameters
XG = 10 Gbits/s PORT
SU = SUPERVISOR
11
G = 10/100/1000 Mbits/s PORT
PORT NUMBERING SCHEME
NA
NA
XG1
Reset = 0
4
1
4
1
49
12
XG0
13
48
14
G47
47
15
G46
16
46
The port number used for MAC source address
learning.
17
G45
45
18
19
G44
44
20
21
22
Description
23
8
24
7
G3
3
25
6
26
G2
5
2
27
4
G1
1
28
3
ET4148-50
29
2
G0
0
30
1
31
0
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