L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 41

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Functional Description
Supervisor Packet Reception
Hardware Actions.
1. Check if close to end of FIFO physical limit.
The first step taken by the ET4148-50 is to determine if the space remaining between the logical end of a receive
FIFO and its physical end (refer to Figure 18 on page 40 for a depiction of the terms) is great enough to accommo-
date a maximum length packet. The following equation is used to make this determination:
If the preceding equation is true, then proceed to step 2. Otherwise, proceed to step 3.
2. Set start-of-packet pointer in packet data structure to the subsequent location.
Here, Supervisor_Rx_Packet.packet_start_ptr[31:2] is set equal to
Supervisor_Rx_Fifo_Ptr_{0..7}.wr_ptr[31:2] + 4 (i.e., the next memory location).
Supervisor_Rx_Packet.packet_start_ptr[31:2] is then written to the supervisor memory location
pointed to by Supervisor_Rx_Fifo_Ptr_{0..7}.wr_ptr[31:2] and the write pointer is advanced
Go to step 4.
3. Set start-of-packet pointer in packet data structure to the start of the FIFO.
If the preceding equation is false, then Supervisor_Rx_Packet.packet_start_ptr[31:2] is set equal to
Supervisor_Rx_Fifo_Limits_{0..7}.rx_fifo_start_ptr[31:2].
Supervisor_Rx_Packet.packet_start_ptr[31:2] is then written to the supervisor memory location
pointed to by Supervisor_Rx_Fifo_Ptr_{0..7}.wr_ptr[31:2] and the write pointer is set equal to
Supervisor_Rx_Fifo_Limits_{0..7}.rx_fifo_start_ptr[31:0].
Continue with step 4.
4. Check FIFO capacity.
The last check is to determine if there is sufficient room between
Supervisor_Rx_Fifo_Ptr_{0..7}.wr_ptr[31:2] and
Supervisor_Rx_Fifo_Limits_{0..7}.rx_fifo_first_ptr[31:2] to store a maximum length packet. The
following equation is used to make this determination
If the preceding equation is false, wait. Otherwise, proceed to step 5.
5. Write packet data.
If the preceding equation is true, then there is sufficient room for a maximum length packet and the packet transfer
commences. Supervisor_Rx_Packet[4..<end of packet>] is written to sequential 32-bit words of super-
visor memory with Supervisor_Rx_Fifo_Ptr_{0..7}.wr_ptr[31:2] advancing after each write. At the com-
pletion of the transfer, Supervisor_Rx_Fifo_Ptr_{0..7}.last_ptr[31:2] is set equal to the value that
Supervisor_Rx_Fifo_Ptr_{0..7}.wr_ptr[31:2] held prior to any writes. This last step marks the first 32-bit
word of the last packet in the receive FIFO.
Whenever Supervisor_Rx_Fifo_Limts_{0..7}.first_ptr[31:2] and
Supervisor_Rx_Fifo_Ptr_{0..7}.last_ptr[31:2] are not equal, then the FIFO is not empty and an indica-
tion to that effect is provided to the supervisor via Supervisor_Rx_Fifo_Status_{0..7}.not_empty.
1.The write pointer (Supervisor_Rx_Fifo_Ptr_{0..7}.wr_ptr[31:2]) may never be advanced by the hardware to be equal to the first
2. If the difference computed in this equation is negative, then the equation is considered to be true.
pointer (Supervisor_Rx_Fifo_Limits_{0..7}.rx_fifo_first_ptr[31:2])
tion, the advancement of the write pointer is delayed until the software has moved the first pointer.
( Supervisor_Rx_Fifo_Limits_{0..7}.rx_fifo_end_ptr[31:0] -
Supervisor_Rx_Fifo_Ptr_{0..7}.wr_ptr[31:2] ) >=
Supervisor_Mode.maximum_packet_length[13:0]
( Supervisor_Rx_Fifo_Limits_{0..7}.rx_fifo_first_ptr[31:2] -
Supervisor_Rx_Fifo_Ptr_{0..7}.wr_ptr[31:2] ) >=
Supervisor_Maximum_Packet_Length.maximum_packet_length[13:0]
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
(continued)
Agere Systems - Proprietary
2
:
.
If advancing the first pointer would cause such a situa-
ET4148-50
1
by 4.
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