L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 241

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Supervisor_Rx_Fifo_Ptr
Description: The pointers used in managing the supervisor’s receive packet FIFOs.
Table 337. Supervisor_Rx_Fifo_Ptr Register Diagram
Table 338. Supervisor_Rx_Fifo_Ptr Field Parameters
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
rx_fifo_last_ptr[31:2]
rx_fifo_wr_ptr[31:2]
0
8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Parameter
Field Name
2
3
4
5
6
Figure 254. Supervisor_Rx_Fifo_Ptr Register Parameters
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
9
0x000c_c400
10
Agere Systems - Proprietary
11
Value
Instances = 1
Instances = 1
Mode = R/W
Mode = R/W
Parameters
Offset = 4.0
Offset = 8.0
NA
64
1
8
8
8
12
rx_fifo_last_ptr[31:2]
rx_fifo_wr_ptr[31:2]
13
14
15
16
17
Defines the location within supervisor memory of
the last complete packet stored by the ET4148-50
in supervisor memory. This pointer is maintained by
the ET4148-50 and interpreted by the supervisor. It
lets the supervisor know which packet is the last in
the FIFO.
This register is for informational purposes only and
need not be accessed during normal operation.
rx_fifo_wr_ptr[31:2] reflects the supervisor
address currently or most recently addressed by the
ET4148-50 during receive packet transfer opera-
tions.
18
19
20
21
22
23
8
Description
24
7
25
6
26
5
27
4
28
3
29
2
ET4148-50
30
1
0
0
31
0
0
0
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