L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 91

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Acl_Protocol_Ace_Map_Table
Description: This table converts ACE map index values derived from protocol indexes into ACE maps.
Table 82. Acl_Protocol_Ace_Map_Table Register Parameters
Table 83. Acl_Protocol_Ace_Map_Table Field Parameters
This table is addressed by Acl_Protocol_Ace_Map_Index_Table.protocol_ace_map_index[6:0] and
returns the 64-bit ACE map value for the associated packet protocol. An ACE map is a vector that identifies all of
the ACEs for which the associated protocol registers a match.
The following figure shows where this table fits in the ACL processing pipeline.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
priority_ace_map[63:0]
0
4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Parameter
Field Name
2
3
4
5
Figure 63. Acl_Protocol_Ace_Map_Table Register Diagram
6
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
9
Figure 64. ACL Processing Pipeline
10
Agere Systems - Proprietary
11
Mode = R/W
Parameters
0x0004_1400
Offset = 0.0
ACL Index
12
priority_ace_map[63:32]
Value
1024
priority_ace_map[31:0]
128
NA
13
1
8
8
14
15
ACE Map Index Table
16
ACL Result Tables
Protocol Number
ACE Map Table
Protocol Table
17
The ACE map value.
ACL Result
Encoder
18
19
ACE Map
ACE Index
20
21
22
Description
23
8
24
7
25
6
26
5
27
4
28
3
ET4148-50
29
2
30
1
31
0
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