L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 232

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L-ET4148-50C-DB

Manufacturer Part Number
L-ET4148-50C-DB
Description
Manufacturer
LSI
Datasheet

Specifications of L-ET4148-50C-DB

Lead Free Status / RoHS Status
Supplier Unconfirmed
ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Supervisor_Int
Description: Supervisor related interrupts.
Table 321. Supervisor_Int Register Parameters
Table 322. Supervisor_Int Field Parameters
This register presents those indications that have not been masked by Supervisor_Int_Mask.
For the definitions of the various interrupt bits, see Supervisor_Ind, page 228.
232
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
int[15:0]
0
Field Name
Parameter
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
2
3
4
5
(continued)
6
Figure 245. Supervisor_Int Register Diagram
7
8
9
Instances = 1
Offset = 0.16
Parameters
Mode = RO
Agere Systems - Proprietary
10
0x000c_c458
11
Value
12
NA
NA
4
1
4
1
13
14
15
Various supervisor interrupts.
16
17
18
19
20
21
22
Description
23
8
Preliminary Data Sheet
24
7
25
6
26
5
Agere Systems Inc.
27
4
28
3
April 2006
29
2
30
1
31
0

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