L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 236

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Supervisor_Invalid_Addr
Description: Provides supervisor with the address that resulted in an invalid address indication.
Table 329. Supervisor_Invalid_Addr Register Parameters
Table 330. Supervisor_Invalid_Addr Field Parameters
This register captures and presents the address of a supervisor access cycle that failed to address a valid location.
Once an address value is captured, this register ignores all future invalid address events until
Supervisor_Ind.invalid_addr has been cleared.
236
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
supervisor_invalid_addr[31:2]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
Parameter
Field Name
1
2
3
4
5
Figure 249. Supervisor_Invalid_Addr Register Diagram
6
(continued)
7
8
9
0x000c_c468
Instances = 1
10
Mode = R/W
Parameters
Offset = 0.0
Agere Systems - Proprietary
Value
11
supervisor_invalid_addr[31:2]
NA
NA
4
1
4
1
12
13
14
15
16
The location of an invalid address access by the
supervisor.
17
18
19
20
21
22
Description
23
8
24
7
Preliminary Data Sheet
25
6
26
5
Agere Systems Inc.
27
4
28
3
29
2
April 2006
30
1
0
31
0
0