L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 125

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Layer_2_Src_Mirror_Map
Description: Identifies those ports whose receive traffic is to be mirrored.
Table 149. Layer_2_Src_Mirror_Map Register Parameters
Table 150. Layer_2_Src_Mirror_Map Field Parameters
This port map identifies those ports whose receive traffic is to be copied to the mirror port. If a packet’s receive
port’s corresponding bit in src_mirror_map[57:0] is asserted, then the packet is copied to the mirror port.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
src_mirror_map[57:0]
REFERENCE
0
4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
PORT
1
Parameter
Field Name
2
SU7
57
3
SU6
4
56
5
6
Figure 111. Layer_2_Src_Mirror_Map Register Diagram
7
SU1
51
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
SU0
9
50
PORT NUMBERING SCHEME
Figure 112. Port Numbering Scheme
10
XG1
0x000c_4658
49
Agere Systems - Proprietary
Instances = 1
Mode = R/W
Parameters
11
Offset = 0.6
Reset = 0
Value
XG0
48
NA
NA
12
1
8
1
8
13
G47
src_mirror_map[31:0]
47
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
14
G46
46
15
G45
45
16
src_mirror_map[57:32]
The source mirror map.
17
G44
44
18
19
20
21
G3
3
22
Description
23
8
G2
2
24
7
G1
1
25
6
G0
0
26
5
27
4
28
3
ET4148-50
29
2
30
1
31
0
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