MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 118

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Figure 54: READ Latency (AL = 5, CL = 6)
Mode Register 2 (MR2)
Figure 55: Mode Register 2 (MR2) Definition
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
BC4
DQS, DQS#
Command
CK#
DQ
CK
ACTIVE n
T0
Notes:
READ n
The mode register 2 (MR2) controls additional functions and features not available in
the other mode registers. These additional functions are CAS WRITE latency (CWL),
AUTO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC
ODT (R
is programmed via the MRS command and will retain the stored information until it is
programmed again or until the device loses power. Reprogramming the MR2 register will
not alter the contents of the memory array, provided it is performed correctly. The MR2
register must be loaded when all banks are idle and no data bursts are in progress, and
the controller must wait the specified time
quent operation.
1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to “0.”
T1
M15
0
0
1
1
t RCD (MIN)
M14
0
1
0
1
TT
_
M10
Mode register set 0 (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
WR
0
0
1
1
AL = 5
NOP
). These functions are controlled via the bits shown in Figure 55. The MR2
T2
Mode Register
M9
0
1
0
1
R
Dynamic ODT
TT
_
( R
Reserved
WR
RZQ/4
RZQ/2
TT
0 1
BA2
16
disabled
_
RL = AL + CL = 11
WR
)
1
15
BA1
NOP
T6
14
0
BA0
118
0 1
13
M7
A13
0
1
0 1
12
Self Refresh Temperature
A12 A11
Extended (0°C to 95°C)
M6
Normal (0°C to 85°C)
0
1
0 1
11
Enabled: Automatic
Disabled: Manual
CL = 6
Auto Self Refresh
R
Micron Technology, Inc., reserves the right to change products or specifications without notice.
10
TT
(Optional)
A10
T11
NOP
_
WR
9
t
A9
MRD and
0 1
8
A8
Indicates a Break in
Time Scale
SRT
7
A7 A6 A5 A4 A3
2Gb: x4, x8, x16 DDR3 SDRAM
ASR
6
M5
NOP
0
0
0
0
1
1
1
1
T12
t
5
MOD before initiating a subse-
CWL
M4
0
0
1
1
0
0
1
1
4
DO
M3
n
0
1
0
1
0
1
0
1
3
6 CK (2.5ns > t CK ≥ 1.875ns)
7 CK (1.875ns > t CK ≥ 1.5ns)
0 1 0 1 0 1
8 CK (1.5ns > t CK ≥ 1.25ns)
2
CAS Write Latency (CWL)
©2006 Micron Technology, Inc. All rights reserved.
A2 A1 A0
Transitioning Data
n + 1
DO
5 CK ( t CK ≥ 2.5ns)
1
Reserved
Reserved
Reserved
Reserved
NOP
T13
0
n + 2
DO
Address bus
Mode register 2 (MR2)
Operations
n + 3
DO
Don’t Care
NOP
T14