MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 162

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Table 78:
Table 79:
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D5.fm - Rev G 2/09 EN
Symbol
ODTL on
ODTL off
t
t
ODTH4
ODTH8
t
t
AONPD
AOFPD
AON
AOF
MR1[9, 6, 2]
110 and 111
000–101
000–101
000
000
Truth Table – ODT (Nominal)
Note 1 applies to the entire table
ODT Parameter
ODT minimum HIGH time after ODT
ODT turn-off relative to ODTL off
ODT asynchronous turn off delay
ODT turn-on relative to ODTL on
ODT asynchronous turn on delay
ODT synchronous turn off delay
ODT synchronous turn on delay
ODT minimum HIGH time after
Notes:
assertion or write (BC4)
ODT Pin
Description
completion
completion
write (BL8)
X
0
1
0
1
1. Assumes dynamic ODT is disabled (see “Dynamic ODT” on page 163 when enabled).
2. ODT is enabled and active during most writes for proper termination, but it is not illegal to
3. ODT must be disabled during reads. The R
Nominal ODT resistance R
page 115. The R
mentioned. DDR3 SDRAM supports multiple R
can be 2, 4, 6, 8, or 12 and RZQ is 240Ω. R
the DRAM is initialized, calibrated, and not performing read access or when it is not in
self refresh mode.
Write accesses use R
during writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 81 on page 164).
ODT timings are summarized in Table 79, as well as listed in Table 56 on page 70.
Examples of nominal ODT timing are shown in conjunction with the synchronous mode
of operation in “Synchronous ODT Mode” on page 168.
have it off during writes.
ODT is applicable if enabled.
R
TT
DRAM Termination State
R
R
_
R
R
NOM
TT
TT
TT
TT
_
TT
_
_
_
NOM
NOM
NOM
NOM
_
reserved, ODT on or off
NOM
TT
enabled, ODT off
disabled, ODT off
enabled, ODT on
disabled, ODT on
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
ODT registered HIGH
or write registration
_
Write registration
NOM
termination value applies to the output pins previously
with ODT HIGH
with ODT HIGH
Completion of
Completion of
TT
Begins at
ODTL off
ODTL on
if dynamic ODT (R
_
162
NOM
is defined by MR1[9, 6, 2], as shown in Figure 53 on
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TT
TT
_
ODT registered
ODT registered
_
NOM
R
R
NOM
Defined to
TT
TT
Any valid except self refresh, read
Any valid except self refresh, read
_
_
TT
R
R
TT
R
R
ON
OFF
TT
LOW
LOW
TT
TT
TT
termination is allowed any time after
2Gb: x4, x8, x16 DDR3 SDRAM
value is restricted during writes. Dynamic
_
_
_
_
NOM
_
_
WR
±
OFF
OFF
±
ON
ON
t
t
AON
AOF
) is disabled. If R
On-Die Termination (ODT)
values based on RZQ/n where n
DRAM State
Any valid
Any valid
Illegal
Definition for All
DDR3 Speed Bins
©2006 Micron Technology, Inc. All rights reserved.
See Table 56 on
0.5
CWL + AL - 2
CWL + AL - 2
t
page 70
CK ±0.2
6
4
1–9
1–9
t
t
CK
CK
TT
_
NOM
t
CK
is used
Notes
Units
t
t
t
t
t
2
3
2
3
ns
ns
ps
CK
CK
CK
CK
CK