MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 121

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Mode Register 3 (MR3)
Figure 57: Mode Register 3 (MR3) Definition
MULTIPURPOSE REGISTER (MPR)
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
Notes:
The mode register 3 (MR3) controls additional functions and features not available in
the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR).
This function is controlled via the bits shown in Figure 57. The MR3 is programmed via
the LOAD MODE command and retains the stored information until it is programmed
again or until the device loses power. Reprogramming the MR3 register will not alter the
contents of the memory array, provided it is performed correctly. The MR3 register must
be loaded when all banks are idle and no data bursts are in progress, and the controller
must wait the specified time
1. MR3[16 and 13:4] are reserved for future use and must all be programmed to “0.”
2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.
3. Intended to be used for READ synchronization.
The MULTIPURPOSE REGISTER function is used to output a predefined system timing
calibration bit sequence. Bit 2 is the master bit that enables or disables access to the
MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic
concept of the multipurpose register is shown in Figure 58 on page 122.
If MR3[2] is a “0,” then the MPR access is disabled, and the DRAM operates in normal
mode. However, if MR3[2] is a “1,” then the DRAM no longer outputs normal read data
but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to “00,” then a
predefined read pattern for system calibration is selected.
To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1 (see Table 72 on
page 122). Prior to issuing the MRS command, all banks must be in the idle state (all
banks are precharged, and
or RDAP commands are redirected to the multipurpose register. The resulting operation
when either a READ or a RDAP command is issued, is defined by MR3[1:0] when the
MPR is enabled (see Table 73 on page 123). When the MPR is enabled, only READ or
RDAP commands are allowed until a subsequent MRS command is issued with the MPR
disabled (MR3[2] = 0). Power-down mode, self refresh, and any other nonREAD/RDAP
command is not allowed during MPR enable mode. The RESET function is supported
during MPR enable mode.
M15
0
0
1
1
M14
0
1
0
1
0 1
16
BA2
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
Mode register set (MR0)
15
1
BA1
Mode Register
1
14
BA0
0 1 0 1
13
A13
12
A12 A11
0 1 0 1 0 1 0 1
11
10
A10
t
RP is met). When the MPR is enabled, any subsequent READ
t
121
MRD and
9
A9
M2
0
1
8
A8
Normal DRAM operations 2
0 1
7
Dataflow from MPR
A7 A6 A5 A4 A3
0 1
MPR Enable
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
6
MOD before initiating a subsequent operation.
0 1 0 1 0 1
5
4
2Gb: x4, x8, x16 DDR3 SDRAM
3
MPR
2
A2 A1 A0
MPR_RF
1
M1
0
0
1
1
M0
0
0
1
0
1
©2006 Micron Technology, Inc. All rights reserved.
Predefined pattern 3
MPR READ Function
Address bus
Mode register 3 (MR3)
Reserved
Reserved
Reserved
Operations