MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 79

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Command and Address Setup, Hold, and Derating
Table 57:
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D3.fm - Rev G 2/09 EN
t
t
t
IH (base) DC100
IS (base) AC175
IS (base) AC150
Symbol
Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based
DDR3-800
200
350
275
The total
sheet
page 70) to the Δ
page 80), respectively. Example:
sition, the input signal has to remain above/below V
(see Table 59 on page 80).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V
tion), a valid input signal is still required to complete the transition and to reach V
V
between the values listed in Table 59 on page 80 and Table 60 on page 81, the derating
values may be obtained by linear interpolation.
Setup (
last crossing of V
rate for a falling signal is defined as the slew rate between the last crossing of V
and the first crossing of V
nominal slew rate line between the shaded “V
slew rate for derating value (see Figure 32 on page 82). If the actual signal is later than the
nominal slew rate line anywhere between the shaded “V
rate of a tangent line to the actual signal from the AC level to the DC level is used for
derating value (see Figure 34 on page 84).
Hold (
last crossing of V
rate for a falling signal is defined as the slew rate between the last crossing of
V
nominal slew rate line between the shaded “DC-to-V
slew rate for derating value (see Figure 33 on page 83). If the actual signal is earlier than
the nominal slew rate line anywhere between the shaded “DC-to-V
slew rate of a tangent line to the actual signal from the DC level to the V
used for derating value (see Figure 35 on page 85).
IL
IH
(
(
AC
DC
t
) (see Figure 13 on page 44 for input signal requirements). For slew rates which fall
t
IS (base) and
IH) nominal slew rate for a rising signal is defined as the slew rate between the
) MIN and the first crossing of V
t
IS) nominal slew rate for a rising signal is defined as the slew rate between the
t
DDR3-1066
IS (setup time) and
125
275
200
t
REF
IL
IS and Δ
(
DC
(
t
IH (base) values (see Table 57; values come from Table 56 on
DC
) MAX and the first crossing of V
) and the first crossing of V
IL
t
DDR3-1333
IH derating values (see Table 58 on page 80 and Table 59 on
(
AC
190
79
t
140
) MAX. If the actual signal is always earlier than the
65
IH (hold time) required is calculated by adding the data
t
IS (total setup time) =
IH
[
REF
AC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
]/V
(
DDR3-1600
DC
IL
). If the actual signal is always later than the
[
REF
170
120
45
AC
] at the time of the rising clock transi-
(
2Gb: x4, x8, x16 DDR3 SDRAM
DC
IH
(
IH
)-to-AC region,” use the nominal
REF
AC
REF
(
t
AC
) MIN. Setup (
IS (base) + Δ
(
REF
DC
(
)/V
DC
(
) region,” use the nominal
Units
DC
). Hold (
IL
ps
ps
ps
(
©2006 Micron Technology, Inc. All rights reserved.
)-to-AC region,” the slew
AC
) for some time
Speed Bin Tables
REF
t
IS. For a valid tran-
t
IH) nominal slew
t
IS) nominal slew
(
DC
REF
V
V
V
) region,” the
Reference
IH
IH
IH
(
(
(
(
DC
AC
AC
DC
) level is
)/V
)/V
)/V
REF
IL
IL
IL
t
IH
(
(
(
(
VAC
DC
AC
AC
DC
(
AC
)
)
)
)
)/