20-668-0003 Rabbit Semiconductor, 20-668-0003 Datasheet - Page 187

• Manufacturer Part Number: 20-668-0003
• Description: IC CPU RABBIT2000 30MHZ 100PQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 20-668-0003

• Processor Type: Rabbit 2000 8-Bit
• Speed: 30MHz
• Voltage: 2.7V, 3V, 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 30 MHz
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 40
• Number Of Timers: 8 & 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 20-668-0003; 316-1062

18.10 8-bit Arithmetic and Logical Ops
Chapter 18 Rabbit Instructions
ADD IY,yy
ADD SP,d
AND HL,DE
AND IX,DE
AND IY,DE
BOOL HL
BOOL IX
BOOL IY
DEC IX
DEC IY
DEC ss
INC IX
INC IY
INC ss
MUL
OR HL,DE
OR IX,DE
OR IY,DE
RL DE
RR DE
RR HL
RR IX
RR IY
SBC HL,ss
Instruction
ADC A,(HL)
ADC A,(IX+d)
ADC A,(IY+d)
ADC A,n
ADC A,r
ADD A,(HL)
ADD A,(IX+d)
ADD A,(IY+d)
ADD A,n
ADD A,r
AND (HL)
AND (IX+d)
AND (IY+d)
AND n
AND r
CP* (HL)
CP* (IX+d)
CP* (IY+d)
4
4
2
4
4
2
4
4
4
4
2
4
4
2
12
2
4
4
2
2
2
4
4
4
clk
5
9
9
4
2
5
9
9
4
2
5
9
9
4
2
5
9
9
f
f
fr
f
f
fr
f
f
r
r
fr
f
f
fr
fr
fr
f
f
fr
A
fr s * * V *
fr s * * V *
fr s * * V *
fr
fr
fr s * * V *
fr s * * V *
fr s * * V *
fr
fr
fr s * * L 0
fr s * * L 0
fr s * * L 0
fr
fr
f
f
f
I S Z V C
s * * V *
s * * V *
s * * V *
- - - *
- - - *
* * L 0
* * L 0
* * L 0
* * 0 0
* * 0 0
* * 0 0
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
* * L 0
* * L 0
* * L 0
* * L *
* * L *
* * L *
* * L *
* * L *
* * V *
* * V *
* * V *
* * V *
* * V *
* * L 0
* * L 0
IY = IY + yy
DE, IY, SP
SP = SP + d -- d=0 to 255
HL = HL & DE
IX = IX & DE
IY = IY & DE
if (HL != 0) HL = 1,
if (IX != 0) IX = 1
if (IY != 0) IY = 1
IX = IX - 1
IY = IY - 1
ss = ss - 1 -- ss= BC,
DE, HL, SP
IX = IX + 1
IY = IY + 1
ss = ss + 1 -- ss= BC,
DE, HL, SP
HL:BC = BC * DE, signed
32 bit result. DE unchanged
HL = HL | DE -- bitwise or
IX = IX | DE
IY = IY | DE
{CY,DE} = {DE,CY} --
left shift with CF
{DE,CY} = {CY,DE}
{HL,CY} = {CY,HL}
{IX,CY} = {CY,IX}
{IY,CY} = {CY,IY}
HL=HL-ss-CY
(cout if (ss-CY)>hl)
Operation
A = A + (HL) + CF
A = A + (IX+d) + CF
A = A + (IY+d) + CF
A = A + n + CF
A = A + r + CF
A = A + (HL)
A = A + (IX+d)
A = A + (IY+d)
A = A + n
A = A + r
A = A & (HL)
A = A & (IX+d)
A = A & (IY+d)
A = A & n
A = A & r
A - (HL)
A - (IX+d)
A - (IY+d)
set flags to match HL
-- yy=BC,
181