20-668-0003 Rabbit Semiconductor, 20-668-0003 Datasheet - Page 64

• Manufacturer Part Number: 20-668-0003
• Description: IC CPU RABBIT2000 30MHZ 100PQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 20-668-0003

• Processor Type: Rabbit 2000 8-Bit
• Speed: 30MHz
• Voltage: 2.7V, 3V, 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 30 MHz
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 40
• Number Of Timers: 8 & 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 20-668-0003; 316-1062

5.4 Bus Timing
The external bus has essentially the same timing for memory cycles or I/O cycles. A
memory cycle begins with the chip select and the address lines. One clock later, the out-
put enable is asserted for a read. The output data and the write enable are asserted for a
write.
In some cases, the timing shown in Figure 5-4 may be prefixed by a false memory access
during the first clock, which is followed by the access sequence shown in Figure 5-4. In
this case, the address and often the chip select will change values after one clock and
assume the final values for the memory to be actually accessed. Output enable and write
enable are always delayed by one clock from the time the final, stable address and chip
select are enabled. Normally the false memory access attempts to start another instruction
access cycle, which is aborted after one clock when the processor realizes that a read data
or write data bus cycle is needed. The user should not attempt a design that uses the chip
select or a memory address as a clock or state changing signal without taking this into con-
sideration.
58
Notes:
Read may have no wait states.
Write cycles and I/O read cycles have at least 1 wait state. Clock
may be asymmetric if clock doubler used. I/O chip select avail-
able on port E as option.
T1
Tw
Figure 5-4. Bus Timing Read and Write
T2
valid
Address (20 for memory, 16 for I/O)
Data for write 3-s drive starts at end of T1
/OEn or /IORD and /BUFEN (/BUFEN rd or wr)
Data for read
/WEn or /IOWR
/IOCSn or /CSn
Rabbit 2000 Microprocessor User’s Manual