20-668-0003 Rabbit Semiconductor, 20-668-0003 Datasheet - Page 87
![IC CPU RABBIT2000 30MHZ 100PQFP](/photos/6/76/67658/316-100-pqfp_sml.jpg)
20-668-0003
Manufacturer Part Number
20-668-0003
Description
IC CPU RABBIT2000 30MHZ 100PQFP
Manufacturer
Rabbit Semiconductor
Datasheet
1.20-668-0003.pdf
(228 pages)
Specifications of 20-668-0003
Processor Type
Rabbit 2000 8-Bit
Speed
30MHz
Voltage
2.7V, 3V, 3.3V, 5V
Mounting Type
Surface Mount
Package / Case
100-MQFP, 100-PQFP
Data Bus Width
8 bit
Maximum Clock Frequency
30 MHz
Operating Supply Voltage
0 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
40
Number Of Timers
8 & 10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
20-668-0003
316-1062
316-1062
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
20-668-0003
Manufacturer:
Rabbit Semiconductor
Quantity:
10 000
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The code to do this may also hit the watchdog with a 0.25-second period to speed up the
reset. Such watchdog code must be written so that it is highly unlikely that a crash will
incorporate the code and continue to hit the watchdog in an endless loop. The following
suggestions will help.
1. Place a jump to self before the entry point of the watchdog hitting routines. This pre-
2. Before calling the routine, set a data byte to a special value and then check it in the rou-
3. Maintain data corruption flags and/or checksums. If these go wrong, go into an endless
Chapter 7 Miscellaneous I/O Functions
7:0
vents entry other than by a direct call or jump to the routine.
tine to make sure the call came from the right caller. If not, go into an endless loop with
interrupts disabled.
loop with interrupts off.
Bit(s)
Table 7-9. Watchdog Timer Test Register (WDTTR adr = 0x09)
0x51
0x52
0x53
0x54
other
Value
Clock the least significant byte of the WDT timer from the peripheral
clock. (Intended for chip test and code 0x54 below only.)
Clock the most significant byte of the WDT timer from the peripheral
clock. (Intended for chip test and code 0x54 below only.)
Clock both bytes of the WDT timer, in parallel, from the peripheral clock.
(Intended for chip test and code 0x54 below only.)
Disable the WDT timer. This value, by itself, does not disable the WDT
timer. Only a sequence of two writes, where the first write is 0x51, 0x52 or
0x53, followed by a write of 0x54, actually disables the WDT timer. The
WDT timer will be re-enabled by any other write to this register.
Normal clocking (32 kHz oscillator) for the WDT timer. This is the
condition after reset.
Description
81
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