20-668-0003 Rabbit Semiconductor, 20-668-0003 Datasheet - Page 223

• Manufacturer Part Number: 20-668-0003
• Description: IC CPU RABBIT2000 30MHZ 100PQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 20-668-0003

• Processor Type: Rabbit 2000 8-Bit
• Speed: 30MHz
• Voltage: 2.7V, 3V, 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 30 MHz
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 40
• Number Of Timers: 8 & 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 20-668-0003; 316-1062

unless the station is very weak, in which case the interference will be seen as noise distrib-
uted over the screen.
A more important change in timing is that the memory access time will be shortened. The
shortening with the clock doubler enabled and zero wait states is a maximum of 6 ns in the
normal mode and 9 ns in the strong mode. Only one of the 2 clocks in a memory cycle will
be shortened.
Figure B-3. Clock Spectrum Spreader Example
If the clock doubler is not enabled, then the maximum shortening will be 9 ns in the nor-
mal mode and 18 ns in the strong mode. Figure B-3 assumes that the combined address
out and data setup in is 12 ns. The time from clock to output enable is assumed to be 5 ns.
The maximum asymmetry of the clock is assumed to be 52-48%, which shortens one
clock by 4% and lengthens the other by 4% if the clock is doubled.
Early output enable is enabled by default on the Rabbit 2000C, but may be disabled. The
clock low time is controlled by the clock doubler control register, and is assumed to be a
minimum of 14 ns in the above example. Also the maximum clock speed from the exam-
ple with the spreader enabled and 55 ns memory with 25 ns output enable is 25.8 MHz. At
29.49 MHz the memory access must be 50 ns, and the spectrum spreader must be turned
off, or a wait state must be added. Operation with a doubled clock and the spreader
enabled at 29.49 MHz is only allowed for T < 70°C and V > 4.75 V since the instanta-
neous clock frequency bursts to 38.5 MHz when the spectrum spreader and clock asym-
metry together produce maximum shortening of a clock cycle.
Appendix B Rabbit 2000 Revisions
217