LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 3

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
DC and Switching Characteristics
Programmable I/O Cells (PIC) ......................................................................................................................... 2-29
PIO ................................................................................................................................................................... 2-31
DDR Memory Support...................................................................................................................................... 2-35
sysI/O Buffer .................................................................................................................................................... 2-40
SERDES and PCS (Physical Coding Sublayer)............................................................................................... 2-46
IEEE 1149.1-Compliant Boundary Scan Testability......................................................................................... 2-48
Device Configuration........................................................................................................................................ 2-48
Density Shifting ................................................................................................................................................ 2-49
Absolute Maximum Ratings ............................................................................................................................... 3-1
Recommended Operating Conditions ................................................................................................................ 3-1
Hot Socketing Specifications.............................................................................................................................. 3-2
DC Electrical Characteristics.............................................................................................................................. 3-3
LatticeECP2 Supply Current (Standby).............................................................................................................. 3-4
LatticeECP2M Supply Current (Standby)........................................................................................................... 3-5
LatticeECP2 Initialization Supply Current .......................................................................................................... 3-6
LatticeECP2M Initialization Supply Current ....................................................................................................... 3-7
SERDES Power Supply Requirements (LatticeECP2M Family Only) ............................................................... 3-8
SERDES Power (LatticeECP2M Family Only)................................................................................................... 3-8
sysI/O Recommended Operating Conditions..................................................................................................... 3-9
sysI/O Single-Ended DC Electrical Characteristics.......................................................................................... 3-10
sysI/O Differential Electrical Characteristics .................................................................................................... 3-11
Typical Building Block Function Performance.................................................................................................. 3-17
LatticeECP2/M DSP Performance .......................................................................................................... 2-29
Input Register Block ................................................................................................................................ 2-31
Output Register Block ............................................................................................................................. 2-33
Tristate Register Block ............................................................................................................................ 2-35
Control Logic Block ................................................................................................................................. 2-35
Left and Right Edges............................................................................................................................... 2-35
Bottom Edge ........................................................................................................................................... 2-35
Top Edge................................................................................................................................................. 2-36
DLL Calibrated DQS Delay Block ........................................................................................................... 2-37
Polarity Control Logic .............................................................................................................................. 2-39
DQSXFER............................................................................................................................................... 2-40
sysI/O Buffer Banks ................................................................................................................................ 2-40
Typical sysI/O I/O Behavior During Power-up......................................................................................... 2-43
Supported sysI/O Standards ................................................................................................................... 2-43
Hot Socketing.......................................................................................................................................... 2-45
SERDES Block........................................................................................................................................ 2-46
PCS......................................................................................................................................................... 2-47
SCI (SERDES Client Interface) Bus........................................................................................................ 2-47
Soft Error Detect (SED) Support ............................................................................................................. 2-48
External Resistor..................................................................................................................................... 2-49
On-Chip Oscillator................................................................................................................................... 2-49
LVDS....................................................................................................................................................... 3-11
Differential HSTL and SSTL.................................................................................................................... 3-11
LVDS25E ................................................................................................................................................ 3-12
LVCMOS33D .......................................................................................................................................... 3-12
BLVDS .................................................................................................................................................... 3-13
LVPECL .................................................................................................................................................. 3-14
RSDS ...................................................................................................................................................... 3-15
MLVDS.................................................................................................................................................... 3-16
Pin-to-Pin Performance (LVCMOS25 12mA Drive) ................................................................................ 3-17
Register-to-Register Performance .......................................................................................................... 3-17
2
LatticeECP2/M Family Handbook
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