LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 553

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Figure 10-26. SPI4.2 and DDR Registers Interface Application
DQSDLL and DQSDEL
There is another combination of DLL and Slave Delay Line, DQSDLL and DQSDEL, in the LatticeECP2/M device
family. This pair is similar in design and function to DLL and DLLDEL, but usage is limited to DDR implementation.
For additional information, see TN1102,
DCS (Dynamic Clock Select)
DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock
sources and avoids glitches or runt pulses on the output clock, regardless of where the enable signal is toggled.
There are two DCSs for each quadrant. The outputs of the DCS then reach primary clock distribution via the feed-
lines. Figure 10-27 shows the block diagram of the DCS.
840 Mbps/ 420 MHz
840 Mbps
Data/ CLK
420 MHz
Data
CLK
FD: Fixed Delay
DD: Dynamic Delay
Users can select the delay setting in IPexpress.
Data at Pin
CLK at Pin
Data +
Injection Delay
90
Injection Delay
O
Shift +
LatticeECP2/M sysIO Usage
FD DD
DLL CLKOP
DLLDEL
DCNTL[8:0]
10-29
CLKDIV
1.2 nS
LatticeECP2/M sysCLOCK PLL/DLL
1.2 ns
Guide.
Design and Usage Guide
Logic
Core