LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 546

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
DLL Modes of Operation
Clock Injection Removal Mode (CIDDLLA)
The DLL can be used to reduce clock injection delay (CIDDLLA). Clock injection delay is the delay from the input
pin of the device to a destination element such as a flip-flop. The DLL will add delay to the CLKI input to align CLKI
to CLKFB. If the CLKFB signal comes from the clock tree (CLKOP, CLKOS) then the delay of the DLL and the clock
tree will be removed from the overall clock path. Figure 10-20 shows a circuit example and waveform.
Figure 10-20. Clock Injection Delay Removal via DLL
Clock injection removal mode can also provide a DCNTL port. In this mode, the delay added to the CLKI signal is
output on the DCNTL port so that other input signals can be delayed by the same amount. This is very useful if sev-
eral clocks are used in the same circuit to minimize the number of DLLs required. When using the DCNTL, the DLL
delay will be limited to the range of the DCNTL vector. Therefore, IPexpress will restrict the CLKI rate from 300MHz
to 700MHz.
Time Reference Delay Mode (TRDLLA: 90-Degree Phase Delay)
The Time Reference Delay (TRDDLLA) mode of the DLL is used to calculate 90 degrees of delay to be placed on
the DCNTL vector. This is a useful mode in delaying a clock 90 degrees for use in clocking a DDR type interface.
Figure 10-21 provides a circuit example of this mode.
Figure 10-21. Time Reference Delay Circuit Example
In this mode, CLKI accepts a clock input. The DLL produces a DCNTL vector that will delay an input signal by 90
degrees of a full period of the CLKI signal. This DCNTL vector can then be connected to a Slave Delay Line (DLL-
DELA) to delay the signal by 90 degrees of the full period of CLKI.
CLKI
Clock at
CLOCK TREE
without DLL
CLKOP/CLKOS
at CLOCK TREE
with DLL
CLKI
CLKFB
Data
CLK
CLKI
CIDDLL
ECLK Injection
DLLDEL
TRDLL
Delay
10-22
Clock Injection Delay
DCNTL
CLKOP
ECLK
LatticeECP2/M sysCLOCK PLL/DLL
CLOCK TREE
D
Q
Design and Usage Guide