LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 671

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
The sysDSP Block can be configured as:
• One 36x36 Multiplier
• Four 18x18 Multipliers
• Eight 9x9 Multipliers
Note that a sysDSP block can only be configured in one mode at a time.
sysDSP Block Software
Overview
The sysDSP Block of the LatticeECP2/M device can be targeted in a number of ways.
• The IPexpress™ tool in the ispLEVER or Lattice Diamond™ design software allows the rapid creation of mod-
• The coding of certain functions into a design’s HDL and allowing the synthesis tools to Inference the use of a
• The implementation of designs in The MathWorks
• Instantiation of sysDSP primitives directly in the source code
Targeting sysDSP Block Using IPexpress
IPexpress allows you to graphically specify sysDSP elements. Once the element is specified, a HDL file is gener-
ated, which can be instantiated in a design. IPexpress allows users to configure all ports and set all available
parameters. The following modules target the sysDSP Block in IPexpress:
• MULT (Multiplier)
• MAC (Multiplier Accumulate)
• MULTADDSUB (Multiplier Add/Subtract)
• MULTADDSUBSUM (Multiply Add/Subtract and SUM)
Note: See Appendix B for information about targeting a sysDSP Block using Lattice Diamond design software and
IPexpress.
MULT Module
The MULT Module configures elements to be packed into the sysDSP primitives. The Basic mode screen illustrated
in Figure 14-2 consists of an optional one clock, one clock enable and one reset tied to all registers. Multiple sys-
DSP Blocks can be spanned to accommodate large multiplications. Additional LUTs may be required if multiple
sysDSP blocks are needed. Select Area/Speed to determine the LUT implementation. The input data format can
be selected as Parallel, Shift or Dynamic. The Shift format can only be enabled if inputs are less than 18 bits. The
Shift format enables a sample/shift register, which is useful in applications such as the FIR filter. The Advanced
mode screen, illustrated in Figure 14-3, allows finer control over the register. In the Advanced mode, users can
control each register with independent clocks, clock enables and resets. MULT inputs can be from 2 to 72 bits.
ules implementing sysDSP elements. These modules can then be used in HDL designs as appropriate.
sysDSP block.
DSP design tools will then convert these blocks into HDL as appropriate.
– Basic multiplier, no add/sub/accum/sum blocks
– Two add/sub/accum blocks
– One summation block for adding four multipliers
– Four add/sub blocks
– Two summation blocks
®
Simulink
14-2
®
tool using a Lattice block set. The ispLEVER sys-
sysDSP Usage Guide
LatticeECP2/M