LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 462

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Table 8-23. Simulation Model Locations
Models that are distributed in .zip files need to be decompressed before the model can be used.
Reset Usage in Simulation
If any of the PCS reset signals is not tied to GND, the designer must be careful if the same reset signal is used in
the FPGA core. For example, if one of the reset signals is used to reset both the PCS and a counter in the FPGA
core, and the counter uses txfullclk, the counter will not work. The counter cannot reset itself because txfullck is not
running when the reset is active.
Depending on the reference clock sources, the reset assertion time can vary.
For simulation only, it is recommended to use a minimum active duration of 100ns for PCS reset signals.
16/20-bit Word Alignment
The PCS receiver can not recognize the 16-bit word boundary. With COMMA_ALIGN in 'AUTO' mode, the PCS can
only do BYTE alignment. The 16-bit word alignment should be done in the FPGA fabric and is fairly straight for-
ward. The simulation model works in the same way. It can be enhanced if users implement an alignment scheme
as described below.
For example, if transmit data before at the FPGA interface are:
Then the incoming data in PCS after 8b10b decoder and before rx_gearbox are:
After rx_gearbox, they can become:
Clearly sequence 2 is not aligned. It has one byte offset, but 16/20-bit alignment is needed. Let’s say the special
character 'A' should be always placed in the lower byte.
Flopping one 20-bit data combines with the current 16/20-bit data to form 32/40-bit data as shown below:
YZABCDEFGHIJKLM... (each letter is a byte, 8-bit or 10-bit)
YZABCDEFGHIJKLM....
1. {ZY}{BA}{DC}{FE}{HG}{JI}{LK}....
or
2. {AZ}{CB}{ED}{GF}{IH}{KJ}{ML}...
1. {DCBA}{HGFE}{LKJI}....
Next clock cycle:
{FEDC}{JIHG}{NMLK}....
etc.
Cadence NC-Verilog/VHDL, NC-Sim,
Synposys VCS, Mentor Graphics ModelSim,
Aldec Riviera Pro
Note: Model file names with “revA” are for LatticeECP2M-35 engineering samples only.
^
| **Found the A in lower 10-bit, set the offset to '0', send out aligned
data 'BA'
^
| **send out aligned data 'DC'
Simulator
8-57
ispTools\cae_library\simulation\blackbox
LatticeECP2M SERDES/PCS Usage Guide
Model Location