LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 421

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
LatticeECP2M SERDES/PCS Usage Guide
If a CDR loses lock, the loss-of-lock for that channel is asserted and locking to the reference clock retrains the VCO
in the CDR. When this is achieved, loss-of-lock for that channel is de-asserted and the CDR is switched back over
to lock to the incoming data. The CDR will either remain locked to the data, or will go back out of lock again in which
case the re-training cycle will repeat.
Tx Lane-to-Lane Skew
A control bit, sync_toggle, has been added to reset all the active Tx channels to start serialization with bit0. Most
multi-channel protocol standards have requirements to ensure that the Tx lane-to-lane skew is within a certain
specification. This is to ensure that most of the Rx De-skew (Multi-channel alignment, which is not supported in
hard PCS by Lattice ECP2M) is for channel (trace) de-skewing.
The reset to the Tx serializers is generated either by toggling the sync_toggle control bit or by a transition in PLL
Loss of Lock. The reset is applied to all active Tx serializers. If both these source signals are level, then the Tx seri-
alizers are operating normally.
PCS Functional Setup
®
The LatticeECP2M PCS can be configured for use in various applications. Setup is chosen with the ispLEVER
IPexpress module generation tool which allows the user to select the mode and feature options for the PCS. Option
selections are saved in an auto-configuration file which is subsequently used by the ispLEVER bitstream generator
to write the user selections into the bitstream. To change PCS option selections it is recommended that the user re-
run IPexpress to regenerate a PCS module and create a new auto-configuration file. Some options can be changed
by manually editing the auto-configuration file before running the bitstream generator.
After configuration, PCS options can be changed dynamically by writing to PCS registers via the optional SERDES
Client Interface (SCI) bus. The SERDES Client Interface is soft IP that allows the SERDES/PCS quad to be con-
trolled by registers as opposed to configuration memory cells. A table of control and status registers accessible
through the SCI is provided in the Memory Map section of this document.
Auto-Configuration File
Initial register setup for each PCS mode can be performed by using the autoconfiguration feature in ispLEVER. The
module generator provides an auto-configuration file which contains the quad and channel register settings for the
chosen mode. This file can be referred to for front-end simulation and also can be integrated into the bitstream.
When an auto-configuration file is integrated into the bitstream all the quad and channel registers will be set to val-
ues defined in the auto-configuration file during configuration. The SCI (SERDES Client Interface) is therefore not
needed if all quads are to be set via auto-configuration files. However, the SCI must be included in a design if the
user needs to change control registers or monitor status registers during operation.
Transmit Data
The PCS quad transmit data path consists of 8b10b Encoder and Serializer per channel.
8b10b Encoder
This module implements an 8b10b encoder as described within the IEEE 802.3ae-2002 1000BASE-X specifica-
tion. The encoder performs the 8-bit to 10-bit code conversion as described in the specification, along with main-
taining the running disparity rules as specified. The 8b10b encoder can be bypassed on a per channel basis by
setting the attribute CHx_8B10B to “BYPASS” where x is the channel number.
Serializer
The 8b10b encoded data undergoes parallel to serial conversion and is transmitted off chip via the embedded
SERDES.
Receive Data
The PCS quad receive data path consists of the following sub-blocks per channel: Deserializer, Word Aligner,
8b10b Decoder, Optional Link State Machine, and Optional Receive Clock Tolerance Compensation (CTC) FIFO.
Deserializer
Data is brought on-chip to the embedded SERDES where it goes from serial to parallel.
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