LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 463

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Note: The LSB of a 8/10-bit byte or a 16/20-bit word is always transmitted first and received first.
Switching Between 10XH, 10X and 20X Reference Clock Multiplier Modes Using SCI
Designers can change the bit rates between 10XH, 10X and 20X reference clock multiplier modes using the
SERDES Client Interface. This is a useful feature in a system where different rates are received at times and the
receiver is able to sweep between different rates and lock to one of them. For example, a system can sweep three
different rates of 622Mbps, 1.244Gbps and 2.488Gbps and lock to one of them whichever is received.
There are a few control register bits associated with different rates.
Switching Between 20X to 20XH or 10X to 10XH Mode in 16-Bit Interface
In addition to the control register settings described above, the transmit interface clock(ff_txiclk_chn) input must be
switched from txhalfclk to txqtrclk as described in Table 8-5. ff_rxiclk_chn is not affected in this case. The CDR PLL
will automatically tune to the incoming data rate and provide the correct rxhalfclk as described in Table 8-5.
Contact the Lattice Semiconductor Technical Support Group for detailed information.
Off-Chip AC Coupling
When off-chip AC coupling is required, the recommended capacitor values are shown in Table 8-24.
Table 8-24. Off-chip AC Coupling Capacitor Values
When a DC balanced pattern is used, such as 8b10b encoding, a capacitor of minimum 4.7nF, is required to
reduce the edge degradation.
Data patterns with longer run lengths require larger capacitance values to reduce pattern dependent jitter.
CH_0A[D1]: rate_mode_tx
CH_0B[D1]: rate_mode_rx
QD_13[D6]: refclk_mode[0]
QD_18[D5]: quad_rst
2. {CBAZ}{GFED}{KJIH}....
After the 16/20-bit alignment, the output data are:
{ZY}{BA}{DC}{FE}{HG}{JI}{LK}....
Next clock cycle:
etc.
After the 20-bit alignment, the output data are:
{ZY}{BA}{DC}{FE}{HG}{JI}{LK}....
^
| **Found the A in upper 10-bit, set the offset to '10', send out aligned
{EDCB}{IHGF}{MLKJ}....
data 'BA'
^
| **send out aligned data 'DC'
8b10b
PCI Express rev1.1
Protocol
Min.
4.7
75
Typ.
10
8-58
LatticeECP2M SERDES/PCS Usage Guide
Max.
200
@ 3.125Gbps
Remark
Units
nF
nF