LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 466

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Table 8-26. Reset Controls Description
Power-Down Controls Description
Each Rx and Tx channel can be individually powered-down by a software register bit or a control signal from the
FPGA. The individual channel power-down control bits will only power down selected blocks within the SERDES
macro and the high-speed I/O buffers.
Table 8-27. Power-Down Controls Descriptions
Table 8-28. Reset Pulse Specification
Table 8-29. Power-Down/Power-Up Timing Specification
ffc_quad_rst
ffc_macro_rst
ffc_lane_tx/rx_rst_ch[0:3] lane_tx/rx_rst[0:3]
1. For all channels in the quad running in full-data-rate mode, parallel side clocks are guaranteed to be in-phase.
2. For all channels in the quad running in half-data-rate mode, each channel has a separate divide-by-two circuit. Since there is no mechanism
3. In half-data-rate mode, since there is no guarantee that the parallel side clocks are in phase, this may add channel-to-channel skew to both
ffc_txpwdnb_ch[0:3]
ffc_rxpwdnb_ch[0:3]
ffc_rrst_ch[0:3]
ffc_trst
in the quad to guarantee that these divide by two circuits are in phase after de-assertion of “macrorst”, the PCS design should assume that
the dividers (and therefore the parallel side clocks) are NOT in phase.
transmit and receive sides of a multi-channel link.
FPGA
FPGA
Rest Signal
macropdb
Signal
t
t
t
t
t
MACRORST
RRST
TRST
PWRDN
PWRUP
Parameter
Parameter
tpwdnb[0:3]
rpwdnb[0:3]
quad_rst
macro_rst
Control Register
rrst[0:3]
trst
Register
Macro reset high time
Channel RX reset high time
Quad TX reset high time
Power-down time after macropdb
Power-up tim after macropdb
Active low asynchronous input to the SERDES quad, acts on all channels including
the auxiliary channel. When driven low, it powers down the whole macro including
the transmit PLL. All clocks are stopped and the macro power dissipation is mini-
mized.
Active Low Transmit Channel Power Down – Powers down the serilizer and output
driver.
Active Low Receive Channel Power Down – Powers down CDR, input buffer
(equalizer and amplifier) and loss-of-signal detector.
1, 2, 3
Active high, asynchronous input. Resets all SERDES channels including the
auxiliary channel and PCS. This reset includes macro_rst, txpll, cdr, lane_tx_rst,
and lane_rx_rst.
Active high, asynchronous input to the SERDES quad. Gated with software reg-
ister bit. This reset is for the SERDES block only and TXPLL and CDRPLL are
included.
Active high, asynchronous input. Resets individual TX/RX channel in SB, PCS
core and FB blocks.
Resets loss-of-lock (rlol) and loss-of-signal circuits. Does not reset CDR PLL.
Resets the loss-of-lock of AUX PLL (plol).
Description
Description
8-61
LatticeECP2M SERDES/PCS Usage Guide
Min.
Min.
1
3
3
Description
Description
Typ.
Typ.
Max.
Max.
100
10
Units
Unit
ns
ns
ns
µs
µs