LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 506

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Table 9-3. Power Supplies
Input Reference Voltage (V
Each bank can support up to two separate V
old for the referenced input buffers. The locations of these V
pins can be used as regular I/Os if the bank does not require a V
V
When interfacing to DDR memory, the V
input from the memory. A voltage divider between V
age that is used by the DQS transition detector circuit. This voltage divider is only present on V
able on V
TN1105,
follows the SSTL18_II signaling specification.
Mixed Voltage Support in a Bank
The LatticeECP2/M sysIO buffer is connected to three parallel ratioed input buffers. These three parallel buffers are
connected to V
olds for 3.3V (V
a pin-by-pin basis rather than tracking with V
and is independent of the bank V
and 3.3V ratioed input buffers with fixed thresholds, as well as 2.5V ratioed inputs with tracking thresholds.
Prior to device configuration, the ratioed input thresholds always tracks the bank V
effect after configuration. Output standards within a bank are always set by V
dards that can be mixed in the same bank.
Table 9-4. Mixed Voltage Support
REF1
V
1.2V
1.5V
1.8V
2.5V
3.3V
CCIO
for DDR Memory Interface
LatticeECP2/M High-Speed I/O
REF2
V
V
V
V
1. Refer to
Power Sup-
CC
CCIO
CCAUX
CCJ
1.2V
Yes
Yes
Yes
Yes
Yes
. For more information on the DQS transition detect logic and its implementation, please refer to
CCIO
ply
CCAUX
LatticeECP2/M Family Data Sheet
, V
) and 1.2V (V
CCAUX
1.5V
Yes
Core Power Supply
Power Supply for the I/O and Configuration Banks
Auxiliary Power Supply
Power Supply for JTAG Pins
Input sysIO Standards
and V
CCIO
1.8V
REF1,
Yes
CC
CC
) inputs. This allows the input threshold for ratioed buffers to be assigned on
, giving support for thresholds that track with V
voltage. For example, if the bank V
V
REF1
Interface. DDR1 follows the SSTL25_II signaling specification and DDR2
REF2
Description
CCIO
2.5V
REF
Yes
Yes
Yes
Yes
Yes
input must be used as the reference voltage for the DQS and DQ
for recommended min. and max. values.
)
. This option is available for all 1.2V, 2.5V and 3.3V ratioed inputs
input voltages, V
REF1
3.3V
Yes
Yes
Yes
Yes
Yes
9-5
and GND is used to generate an on-chip reference volt-
REF
REF
1.2V
pins are pre-determined within the bank. These
Yes
REF1
voltage.
and V
1.2V
1.2V/1.5V/1.8V/2.5V/3.3V
3.3V
1.2V/1.5V/1.8V/2.5V/3.3V
CCIO
1.5V
Yes
CCIO
Output sysIO Standards
REF2
is 1.8V, it is possible to have 1.2V
. Table 9-4 shows the sysIO stan-
, that are used to set the thresh-
CCIO
CCIO
1.8V
Value
Yes
LatticeECP2/M sysIO
. This option only takes
as well as fixed thresh-
1
REF1
2.5V
Yes
Usage Guide
it is not avail-
3.3V
Yes