LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 422

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Word Alignment (Byte Boundary Detect)
This module performs the comma codeword detection and alignment operation. The comma character is used by
the receive logic to perform 10-bit word alignment upon the incoming data stream. The word aligner can be
bypassed on a per channel basis by setting attribute CHx_COMMA_ALIGN to “BYPASS” where x is the channel
number. The comma description can be found in section 36.2.4.9 of the 802.3.2002 1000BASE-X specification as
well as section 48.2.6.3, Figure 48-7 of the 10GBASE-X specification.
A number of programmable options are supported within the word alignment module:
• Software enable control (in User Configured - UC mode).
• Ability to set two programmable word alignment characters (typically one for positive and one for negative dispar-
• The first alignment character is defined by the 10-bit value assigned to attribute COMMA_A. This value applies to
• The second alignment character is defined by the 10-bit value assigned to attribute COMMA_B. This value
• The mask register defines which word alignment bits to compare (a ‘1’ in a bit of the mask register means check
When attribute CHx_COMMA_ALIGN is set to ‘AUTO’, one of the protocol based Link State machines will control
word alignment. For more information on the operation of the protocol based Link State Machines, see the Protocol
Specific Link State Machine description below.
8b10b Decoder
The 8b10b decoder implements an 8b10b decoder operation as described with the IEEE 802.3-2002 specification.
The decoder performs the 10-bit to 8-bit code conversion along with verifying the running disparity. The 8b10b
decoder can be bypassed on a per channel basis by setting attribute CHx_8B10B to “BYPASS” where x is the
channel number.
When a code violation is detected, the ff_rxdata receive data is set to 0xEE with ff_rx_k_cntrl_ch set to ‘1’.
Protocol Specific Link State Machine
The PCS implements link state machines for various protocols that are used in various quad modes.
When a protocol specific Link State Machine is selected, that channel’s Link State Machine must be enabled by
setting the protocol CH(0-3)_COMMA_ALIGN to “AUTO”. Selection of the specific Link State Machine that is
enabled in each mode is described below and summarized in Figure 8-7.
The Link State Machine for Gigabit Ethernet is selected when attribute PROTOCOL is “GIGE”. Link synchroniza-
tion is achieved after the successful detection and alignment of the required number of consecutive aligned code
words. The Gigabit Ethernet link synchronization state machine implements the Synchronization State Diagram
shown in Figure 36-9 of the 802.3- 2002 1000BASE-X specification.
In 'G8B10B' and '10-bit SERDES Only' protocols, the Gigabit Ethernet Link State Machine is used when
COMMA_ALIGN is set to 'AUTO'.
Note: UC_Mode refers to 8-bit SERDES Only, 10-bit SERDES Only, SD-SDI, HD-SDI.
ity) and a programmable per bit mask register for alignment compare. Alignment characters and the mask regis-
ter is set on a per quad basis. For many protocols, the word alignment characters can be set to “XXX0000011”
(jhgfiedcba bits for positive running disparity comma character matching code groups K28.1, K28.5, and K28.7)
and “XXX1111100” (jhgfiedcba bits for negative running disparity comma character matching code groups
K28.1, K28.5, and K28.7). However the user can define any bit pattern up to 10 bits long.
all channels in a PCS quad.
applies to all channels in a PCS quad.
the corresponding bit in the word alignment character register). The mask registers defined by the 10-bit value
assigned to attribute COMMA_M. This value applies to all channels in a PCS quad.
8-17
LatticeECP2M SERDES/PCS Usage Guide