LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 4
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LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
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- Download datasheet (18Mb)
Lattice Semiconductor
Pinout Information
Ordering Information
Derating Timing Tables .................................................................................................................................... 3-18
LatticeECP2/M External Switching Characteristics.......................................................................................... 3-19
LatticeECP2/M Internal Switching Characteristics ........................................................................................... 3-28
Timing Diagrams .............................................................................................................................................. 3-30
LatticeECP2/M Family Timing Adders ............................................................................................................. 3-32
sysCLOCK GPLL Timing ................................................................................................................................. 3-35
sysCLOCK SPLL Timing.................................................................................................................................. 3-36
DLL Timing....................................................................................................................................................... 3-37
SERDES High-Speed Data Transmitter (LatticeECP2M Family Only) ............................................................ 3-38
SERDES High Speed Data Receiver (LatticeECP2M Family Only) ................................................................ 3-41
SERDES Power-Down/Power-Up Specification .............................................................................................. 3-43
PCI Express Electrical and Timing Characteristics .......................................................................................... 3-44
LatticeECP2/M sysCONFIG Port Timing Specifications .................................................................................. 3-46
JTAG Port Timing Specifications ..................................................................................................................... 3-51
Switching Test Conditions................................................................................................................................ 3-52
Signal Descriptions ............................................................................................................................................ 4-1
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-4
LatticeECP2 Pin Information Summary, LFE2-6 and LFE2-12 .......................................................................... 4-5
LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35 ........................................................................ 4-7
LatticeECP2 Pin Information Summary, LFE2-50 and LFE2-70 ........................................................................ 4-9
LatticeECP2M Pin Information Summary, LFE2M20 and LFE2M35 ............................................................... 4-11
LatticeECP2M Pin Information Summary, LFE2M50, LFE2M70 and LFE2M100............................................ 4-13
Available Device Resources by Package, LatticeECP2................................................................................... 4-15
Available Device Resources by Package, LatticeECP2M................................................................................ 4-15
LatticeECP2 Power Supply and NC................................................................................................................. 4-16
LatticeECP2 Power Supply and NC (Cont.)..................................................................................................... 4-17
LatticeECP2M Power Supply and NC.............................................................................................................. 4-18
LatticeECP2M Power Supply and NC (Cont.).................................................................................................. 4-19
LatticeECP2M Power Supply and NC (Cont.).................................................................................................. 4-21
LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP ........................................................... 4-22
LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 208 PQFP......................................................... 4-26
LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA .......................................................... 4-31
LFE2-20E/SE Logic Signal Connections: 256 fpBGA ...................................................................................... 4-39
LFE2-12E/SE and LFE2-20E/SE Logic Signal Connections: 484 fpBGA ........................................................ 4-47
LFE2-35E/SE and LFE2-50E/SE Logic Signal Connections: 484 fpBGA ........................................................ 4-60
LFE2-20E/SE and LFE2-35E/SE Logic Signal Connections: 672 fpBGA ........................................................ 4-73
LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA ........................................................ 4-91
LFE2-70E/SE Logic Signal Connections: 900 fpBGA .................................................................................... 4-109
LFE2M-20E/SE and LFE2M-35E/SE Logic Signal Connections: 256 fpBGA ................................................ 4-134
LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA .................................................. 4-141
LFE2M50E/SE Logic Signal Connections: 484 fpBGA .................................................................................. 4-153
LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA .................................................. 4-167
LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA .................................................. 4-184
LFE2M100E/SE Logic Signal Connections: 900 fpBGA ................................................................................ 4-206
LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA .............................................. 4-231
LatticeECP2 Part Number Description............................................................................................................... 5-1
Ordering Information .......................................................................................................................................... 5-1
LatticeECP2 Standard Series Devices, Lead-Free Packaging .......................................................................... 5-5
Input Data Jitter Tolerance...................................................................................................................... 3-41
SERDES External Reference Clock (LatticeECP2M Family Only) ......................................................... 3-43
AC and DC Characteristics ..................................................................................................................... 3-44
LatticeECP2 Standard Series Devices, Conventional Packaging............................................................. 5-2
3
LatticeECP2/M Family Handbook
Table of Contents
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