LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 562
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
- Current page: 562 of 769
- Download datasheet (18Mb)
Lattice Semiconductor
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet:
Revision History
September 2006
February 2006
February 2010
January 2007
January 2007
October 2009
August 2008
March 2009
June 2007
June 2010
April 2006
May 2010
+1-503-268-8001 (Outside North America)
techsupport@latticesemi.com
www.latticesemi.com
Date
Version
01.0
01.1
01.2
01.3
01.4
01.5
01.6
01.7
01.8
01.9
02.0
02.1
Initial release.
Removed unsupported devices, removed DLL SMI phrases, rephrased
DDUTY support due to software incomplete.
Added detailed clock network descriptions.
Added IPexpress GUI quick reference table.
Added LatticeECP2M information throughout.
OSC divider value range updated.
Updated Frequency range.
Described CLKOP and CLKOK synchronous timing relationship with
respective reset signals.
Updated IPexpress Main Window screen shot.
Updated LatticeECP2/M Configuration Tab screen shot.
Updated User Parameters in the Configuration GUI table.
Corrected reference to EXHPLLD in Optional External Capacitor sec-
tion (changed to
Updated GSR section of Attributes.
Updated the LatticeECP2/M PLL Configuration tab screen shot.
Updated the Port names for the LatticeECP2/M PLL Library symbols.
Added LatticeECP2/M PLL Modules section.
Corrected the External Capacitor section.
Removed the DLL operation mode CIMDLLA since it is not available on
LatticeECP2/M.
Updated Power Supplies section.
Updated “DCS Usage with VHDL - Example” code.
Updated Input Clock Sharing (LatticeECP2-50 and LatticeECP2-70) fig-
ure.
Reconciled LOCK description among MachXO, LatticeXP2,
LatticeECP2/M and LatticeECP3.
Specified dedicated clock pins in the Secondary Clocks text section.
Updated for Lattice Diamond design software support.
10-38
EHXPLLD).
LatticeECP2/M sysCLOCK PLL/DLL
Change Summary
Design and Usage Guide
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