LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 636

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Figure 12-22. Read Data Transfer When Using IDDRMFX1A
FPGA Clock (Case 1)
FPGA Clock (Case 2)
DDRCLKPOL = 0
DDRCLKPOL = 1
CLK TO SYNC
CLK TO SYNC
I/O Registers
I/O Registers
DATAVALID
Notes:
1. DDR memory sends DQ aligned to DQS strobe.
2. The DQS strobe is delayed by 90 degress, using the dedicated DQS logic.
3. DQ is now center-aligned to the DQS strobe.
4. PRMBDET is the preamble detect signal generated usin the DQSBUFB primitive. This is used to
5. The first set of I/O registers, A and B, capture data on the positive and negative edges of DQS.
6. I/O register C transfers data such that both data are aligned to the negative edge of DQS.
7. The DDCLKPOL signal generated will determine whether the FPGA clock going into the synchronization registers
8. Registers D and E capture data at the FPGA clock.
9. The data again registers at the FPGA clock to ensure a full clock cycle transfer.
10. The DATAVALID signal goes HIGH when valid data enters the FPGA core. Once DATAVALID is asserted,
DQS at PIN
DQS at IOL
PRMBDET
DQ at PIN
DQ at IOL
generate the DDRCLKPOL signal.
needs to be inverted. The DDRCLKPOL = 0 when the FPGA clock is LOW at the first rising edge of PRMBDET.
So, the clock to the synchronization registers is not inverted. The DDRCLKPOL = 1 when the FPGA clock
is HIGH at the first rising edge of PRMBDET. In this case, the clock to the synchronization register is inverted.
it stays HIGH until the next READ pulse.
QB
QB
QA
QA
C
D
D
B
E
E
A
P0
P0
12-18
N0
P0
N0
P1
P1
P0
N0
N1
P1
N1
P0
P0
N0
N0
P2
P2
N1
P1
P0
N0
N2
N2
P2
P1
P1
N1
N1
P0
N0
High-Speed I/O Interface
N2
P2
P0
N1
N2
P2
P2
N2
P1
N1
LatticeECP2/M
N2
P2