LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 624

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
mended that the bit be programmed “LOW” (more tolerant). For 133 MHz, the LOCK_SENSITIVITY bit can go
either way.
DQSBUFC
This primitive implements the DQS delay and the DQS transition detector logic. Figure 12-7 shows the primitive
symbol.
Figure 12-7. DQSBUFC Symbol
The DQSBUFC is composed of the DQS Delay, the DQS Transition Detect and the DQSXFER block as shown in
Figure 12-8. This block inputs the DQS and delays it by 90 degrees. It also generates the DDR Clock Polarity and
the DQSXFER signal. The preamble detect (PRMBDET) signal is generated from the DQSI input using a voltage
divider circuit.
Figure 12-8. DQSBUFC Function
FPGA CLK
READ
XCLK
DQSI
*DV ~ 170mV for DDR1 (SSTL25 signaling)
*DV ~ 120mV for DDR2 (SSTL18 signaling)
Vref- DV*
Vref
+
-
+
-
PRMBDET
DQSI
CLK
READ
DQSDEL
XCLK
DQSBUFC
12-6
DDRCLKPOL
DATA VALID
DATAVALID
MODULE
PRMBDET
DQSXFER
TRANSITION
DQSDEL
DQSXFER
DETECT
DQSO
DQSC
DELAY
DQS
DQS
High-Speed I/O Interface
LatticeECP2/M
DQSXFER
DATAVALID
DQSO
PRMBDET
DDRCLKPOL
DQSC