LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 474

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Table 8-34. PCS Control Register 4 (QD_03)
Table 8-35. PCS Control Register 5 - CC match 1 LO (QD_04)
Table 8-36. PCS Control Register 6 - CC match 2 LO (QD_05)
Table 8-37. PCS Control Register 7 - CC match 3 LO (QD_06)
Table 8-38. PCS Control Register 8 - CC match 4 LO (QD_07)
Table 8-39. PCS Control Register 9 - CC match HI (QD_08)
Table 8-40. PCS Control Register 10 - UDF comma mask LO (QD_09)
7:6
7:0
Bit
Bit
7:0
Bit
7:0
Bit
5
4
3
2
1
0
7:6
5:4
3:2
1:0
Bit
7:0
Bit
Bit
7:0
cc_match_3 [7:0]
min_ipg_cnt [1:0]
match_4_enable
match_2_enable
cc_match_1 [7:0]
cc_match_4 [7:0]
pfifo_clr_sel
sel_test_clk
asyn_mode
cc_match_4 [9:8]
cc_match_3 [9:8]
cc_match_2 [9:8]
cc_match_1 [9:8]
udf_comma_mask [7:0]
Reserved
cc_match_2 [7:0]
Name
Name
Name
Name
Name
Name
Name
Lower bits of user defined clock compensator skip pattern 3
Minimum IPG to enforce
1 = enable four character skip matching (using match 4, 3, 2, 1)
1 = enable two character skip matching (using match 4,3)
1 = pfifo_clr signal or channel register bit clears the FIFO
0 = pfifo_error internal signal self clears the FIFO
For test only, select asynchronous reset
For test only, select test clock
Lower bits of user defined clock compensator skip pattern 1
Lower bits of user defined clock compensator skip pattern 4
Upper bits of user defined clock compensator skip pattern 4
[9] = Disparity error
[8] = K control
Upper bits of user defined clock compensator skip pattern 3
[9] = Disparity error
[8] = K control
Upper bits of user defined clock compensator skip pattern 2
[9] = Disparity error
[8] = K control
Upper bits of user defined clock compensator skip pattern 1
[9] = Disparity error
[8] = K control
Lower bits of user defined clock compensator skip pattern 2
Lower bits of user defined comma mask
8-69
Description
Description
Description
Description
Description
Description
Description
LatticeECP2M SERDES/PCS Usage Guide
Type
Type
Type
Type
Type
R/W
R/W
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Default
Default
Default
Default
Default
Default
8’hBC
8’hFF
8’h00
2’b01
2’b01
2’b00
2’b00
2’b11
8’h00
8’h50
0
1
0
0
0