LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 531

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Users can program CLKOS with Phase and Duty Cycle options. Phase adjustment can be done in 22.5
Duty Cycle resolution is 1/16th of a period. However, 1/16th and 15/16th duty cycle options are not supported to
avoid minimum pulse violation.
Dynamic Phase Adjustment (DPHASE) and Dynamic Duty Cycle (DDUTY) Select
With LatticeECP2/M device families, users can control the Phase Adjustment and Duty Cycle Select in dynamic
mode. When this mode is selected, both the Phase Adjustment and Duty Cycle Select must be in Dynamic mode.
If only one of the features is to be used in Dynamic mode, the other control inputs can be set with the fixed logic lev-
els desired.
External Capacitor
An optional external capacitor can be used with PLLs to accommodate low frequency input clocks. See the
Optional External Capacitor section of this document for further information.
PLL Inputs and Outputs
CLKI Input
The CLKI signal is the reference clock for the PLL. It must conform to the specifications in the
ily Data Sheet
routing.
RST Input
The PLL reset occurs under two conditions. At power-up an internal power-up reset signal from the configuration
block resets the PLL. The user-controlled PLL reset signal RST is provided as part of the PLL module that can be
driven by an internally generated reset function or a pin. This RST signal resets all internal PLL counters, flip-flops
(including M-Dividers), and the charge pump. The M-Divider reset synchronizes the M-Divider output to the input
clock. When RST goes inactive, the PLL will start the lock-in process, and will take the t
PLL lock. Figure 10-7 shows the timing diagram of the RST Input. RST is active high.
The RESET signal is optional.
Figure 10-7. RST Input Timing Diagram
Figure 10-8 shows the timing relationship between RST and the CLKI Divider Output.
Figure 10-8. RST Input and CLKI Divider Output Timing Diagram (Example: CLKI_DIV = 4)
RST
CLKI
CLKI Divider Output
for the PLL to operate correctly. The CLKI can be derived from a dedicated dual-purpose pin or from
PLL_RST
LOCK
t
RSTREC
1 cycle
t
RST
10-7
t
LOCK
1.5 nS min.
LatticeECP2/M sysCLOCK PLL/DLL
Design and Usage Guide
LOCK
LatticeECP2/M Fam-
time to complete the
o
steps. The