LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 594

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Figure 11-17. PSEUDO DUAL PORT RAM Timing Diagram – with Output Registers
Read Only Memory (ROM)
The EBR blocks in the LatticeECP2/M devices can be configured as Read Only Memory or ROM. IPexpress allows
users to generate the Verilog-HDL or VHDL and the EDIF netlist for the memory size, as per design requirements.
Users are required to provide the ROM memory content in the form of an initialization file.
IPexpress generates the memory module as shown in Figure 11-18.
Figure 11-18. Read-Only Memory Module Generated by IPexpress
The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block,
the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple EBR
blocks can be cascaded, in depth or width (as required to create these sizes).
In ROM mode, the address for the port is registered at the input of the memory array. The output data of the mem-
ory is optionally registered at the output.
WrClockEn
RdClockEn
WrAddress
RdAddress
WrClock
RdClock
Data
Q
t
t
SUADDR_EBR
SUADDR_EBR
t
SUDATA_EBR
t
SUCE_EBR
Data_0
Add_0
OutClockEn
–
t
t
t
OutClock
EBR Based
HADDR_EBR
HADDR_EBR
HDATA_EBR
Address
Reset
Data_1
Add_1
Invalid Data
EBR based Read Only
t
11-20
SUCE_EBR
Memory
ROM
Add_0
LatticeECP2/M Memory Usage Guide
t
HCE_EBR
Q
Add_1
t
COO_EBR
Data_2
Add_2
Data_0
Add_2
t
HCE_EBR
Dat
a_1