LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 620

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LFE2-20E-5FN256I

Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r

Specifications of LFE2-20E-5FN256I

Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFE2-20E-5FN256I
Quantity:
1 831
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 12-1. Typical DDR SDRAM Interface
Figure 12-2. Typical DDR2 SDRAM Interface
The following two figures show the DQ and DQS relationship for memory read and write interfaces.
Figure 12-3. DQ-DQS During READ
(DDR Memory Controller)
(DDR Memory Controller)
(at REG)
(at REG)
(at PIN)
(at PIN)
DQS
DQS
DQ
DQ
FPGA
FPGA
DQS, DQS#
COMMAND
COMMAND
ADDRESS
CONTROL
CLK/CLKN
CLK/CLKN
ADDRESS
CONTROL
DQ<7:0>
DQ<7:0>
DQS
DM
DM
Preamble
CLKP/CLKN
COMMAND
DQS, DQS#
CLKP/CLKN
COMMAND
ADDRESS
CONTROL
CONTROL
ADDRESS
REG and 90
DQS PIN to
Phase Shift
DQ<7:0>
DQ<7:0>
Degree
DQS
DM
DM
12-2
8
X
Y
Z
8
X
Y
Z
Postamble
DQ<7:0>
DQS
DM
ADDRESS
COMMAND
CONTROL
CLK/CLKN
DQ<7:0>
DQS, DQS#
DM
ADDRESS
COMMAND
CONTROL
CLK/CLKN
DDR Memory
DDR Memory
High-Speed I/O Interface
LatticeECP2/M

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