LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 619

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

LatticeECP2/M
High-Speed I/O Interface
June 2010
Technical Note TN1105
Introduction
LatticeECP2™ and LatticeECP2M™ devices support Double Data Rate (DDR) and Single Data Rate (SDR) inter-
faces using the logic built into the Programmable I/O (PIO). SDR applications capture data on one edge of a clock
while the DDR interfaces capture data on both the rising and falling edges of the clock, thus doubling performance.
The LatticeECP2/M I/Os also have dedicated circuitry to support DDR and DDR2 SDRAM memory interfaces. This
technical note details the use of LatticeECP2/M devices to implement both a high-speed generic DDR interface
and DDR and DDR2 memory interfaces.
DDR and DDR2 SDRAM Interfaces Overview
A DDR SDRAM interface will transfer data at both the rising and falling edges of the clock. The DDR2 is the second
generation of the DDR SRDRAM memory.
The DDR and DDR2 SDRAM interfaces rely on the use of a data strobe signal, called DQS, for high-speed opera-
tion. The DDR SDRAM interface uses a single-ended DQS strobe signal, whereas the DDR2 interface uses a dif-
ferential DQS strobe. Figures 12-1 and 12-2 show typical DDR and DDR2 SDRAM interface signals. SDRAM
interfaces are typically implemented with eight DQ data bits per DQS. An x16 interface will use two DQS signals
and each DQS is associated with eight DQ bits. Both the DQ and DQS are bi-directional ports used to both read
and write to the memory.
When reading data from the external memory device, data coming into the device is edge-aligned with respect to
the DQS signal. This DQS strobe signal needs to be phase-shifted 90 degrees before FPGA logic can sample the
read data. When writing to a DDR/DDR2 SDRAM, the memory controller (FPGA) must shift the DQS by 90
degrees to center-align with the data signals (DQ). A clock signal is also provided to the memory. This clock is pro-
vided as a differential clock (CLKP and CLKN) to minimize duty cycle variations. The memory also uses these
clock signals to generate the DQS signal during a read via a DLL inside the memory. Figures 12-3 and 12-4 show
DQ and DQS timing relationships for read and write cycles. For other detailed timing requirements, please refer to
the DDR SDRAM JEDEC specification (JESD79C).
During read, the DQS signal is LOW for some duration after it comes out of tristate. This state is called Preamble.
The state when the DQS is LOW before it goes into Tristate is the Postamble state. This is the state after the last
valid data transition.
DDR SDRAM also requires a Data Mask (DM) signal to mask data bits during write cycles. Note that the ratio of
DQS to data bits is independent of the overall width of the memory. An 8-bit interface will have one strobe signal.
DDR SDRAM interfaces use the SSTL25 Class I/II I/O standards whereas the DDR2 SDRAM interface uses the
SSTL18 Class I/II I/O standards. The DDR2 SDRAM interface also supports differential DQS (DQS and DQS#).
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