LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 754

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
VCCAUX33 supplies power to termination resistors. As a result, noise on VCCAUX33 is directly coupled with the
high-speed I/O, HDIN/HDOUT. A clean FPGA core VCCAUX (power supply) can be used to supply the SERDES
VCCAUX33. Unused SERDES channels are configured in power-down mode by default.
Table 18-2 shows the power supplies and the appropriate voltage levels for each supply.
Table 18-2. Power Supply Description and Voltage Levels
Power Supply Sequencing
There are three main power supplies that are required to power-up the LatticeECP2/M device for proper operation:
V
If the user’s system has the option to design for power sequencing, a practical sequencing is V
V
the LatticeECP2/M “S” version only, V
sequencing considerations should also consider that common supplies are generally tied together to the same rail.
For example, If there is a 3.3V V
ing leakage.
Power Supply Ramp
For the LatticeECP2/M, it is important to make sure that the power supply ramp times stay within a reasonable
range. Each power supply must follow a monotonically clean ramp between the trip points and the minimum
required supply voltage. Slow power supply ramps in the tens of milliseconds to hundreds of milliseconds are criti-
cal to ensure that the transitions around trip points are monotonic.
Multiple transitions through the trip point may cause multiple internal power-on reset sequencing.
Power Estimation
Once the LatticeECP2/M device density, package and logic implementation is decided, power estimation for the
system environment should be determined based on the software Power Calculator provided as part of the isp-
LEVER
By determining these two criteria, LatticeECP2/M power requirements are taken into consideration early in the
design phase.
Configuration
All LatticeECP2/M devices contain two ports that can be used for device configuration. The Test Access Port (TAP),
which supports bit-wide configuration, and the sysCONFIG™ port, which supports both byte-wide and serial con-
figuration.
CC
CCIO8
, V
2. The ability for the system environment and LatticeECP2/M device packaging to be able to support the
1. Power supply budgeting should be based on the maximum of the power-up in-rush current, configuration
CCAUX
. V
®
current or maximum DC and AC current for the given system’s environmental conditions.
specified maximum operating junction temperature.
design tool. When estimating power, the designer should keep two goals in mind:
CC
should reach its minimum voltage value before V
V
V
V
V
V
V
and V
CCTX
CCRX
CCP
CCIB
CCOB
CCAUX33
Supply
CCIO8
. There is no specific power sequencing requirement for the LatticeECP2/M device family.
CCIO
, it should be tied to the same supply as the 3.3V rail for V
1.2V/1.5V
1.2V/1.5V
(Typical)
Voltage
CC
1.2V
1.2V
1.2V
3.3V
must reach its valid minimum value before powering up V
Transmit power supply
Receive power supply
PLL and reference clock buffer power
Input buffer power supply
Output buffer power supply
Termination resistor switching power supply
18-2
CCAUX
LatticeECP2/M Hardware Checklist
and V
Description
CCIO8
reach their minimum values. For
CCAUX
CC
before V
, thus minimiz-
CCAUX
CCAUX
. Power
or