LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 445

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Table 8-14. PCI Express Mode Specific Ports
Receiver Detection
Figure 8-29 shows a Receiver Detection sequence. A Receiver Detection test can be performed on each channel
of a quad independently. Before starting a Receiver Detection test, the transmitter must be put into electrical idle by
setting the ff_pci_ei_en_ch input high. The Receiver Detection test can begin 120 ns after tx_elec_idle is set high
by driving the appropriate ffc_pci_det_en_ch high. This puts the corresponding SERDES Transmit buffer into
receiver detect mode by setting the driver termination to high impedance and pulling both differential outputs to
VCCOB through the high impedance driver termination.
Setting the SERDES Transmit buffer into receiver detect state takes up to 120 ns. After 120ns, the receiver detect
test can be initiated by driving the channel’s ffc_pcie_ct_ch input high for four byte (word) clock cycles. The corre-
sponding channel’s ffc_pcie_done_ch is then cleared asynchronously. After enough time for the receiver detect
test to finish has elapsed (determined by the time constant on the Transmit side), the ffs_pcie_done_ch receiver
detect status port will go high and the Receiver Detect status can be monitored at the ffs_pcie_con_ch port. If at
that time the ffs_pcie_con_ch port is high, then a receiver has been detected on that channel. If, however, the
ffs_pcie_con_ch port is low, then no receiver has been detected for that channel. Once the Receiver Detect test is
complete, ff_pci_ei_en_ch can be deasserted.
Figure 8-29. PCI Express Mode Receiver Detection Sequence (Example for Channel 0)
ffs_pcie_done_ch[3:0]
ffs_pcie_con_ch[3:0]
ffc_pcie_det_en_ch[3:0]
ffc_pcie_ct_ch[3:0]
ffc_ei_en_ch[3:0]
ff_pci_det_en_ch0
ffs_pci_done_ch0
ffs_pcie_con_ch0
ff_pci_ei_en_ch0
ffc_pcie_ct_ch0
Signal
Direction
Previous Receiver
Detection Status
O
O
I
I
I
> 120 ns
Channel
Channel
Channel
Channel
Channel
Class
4 byte
clocks
1 = Far-end receiver detection complete
0 = Far-end receiver detection incomplete
Result of far-end receiver detection.
1 = Far end receiver detected
0 = Far end receiver not detected.
FPGA logic (user logic) informs the SERDES block that it will be request-
ing for a PCI Express Receiver Detection operation.
1=Enable PCI Express Receiver Detect
0 = Normal operation
1 = Request transmitter to do far-end receiver detection
0 = Normal data operation
Control transmission of electrical idle by SERDES transmitter
1 = Force SERDES transmitter to output electrical idle
0 = Normal operation
8-40
LatticeECP2M SERDES/PCS Usage Guide
Invalid During Test
> 2 us*
Description
1 if Receiver detected
0 if Receiver not detected
> 2 ns