LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 603

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
Let us assume that we start to write into the FIFO_DC to fill it. The write operation is controlled by WrClock and
WrEn, however it takes extra RdClock cycles for de-assertion of the Empty and Almost Empty flags.
On the other hand, de-assertion of Full and Almost Full result in the reading out of the data from the FIFO_DC. It
takes extra WrClock cycles, after reading this data, for the flags to come out.
With this in mind, let us look at the FIFO_DC without output registers waveforms. Figure 11-30 shows the operation
of the FIFO_DC when it is empty and the data starts to be written into it.
Figure 11-30. FIFO_DC without Output Registers, Start of Data Write Cycle
The WrEn signal must be high to start writing into the FIFO_DC. The Empty and Almost Empty flags are high to
begin and Full and Almost full are low.
When the first data is written into the FIFO_DC, the Empty flag de-asserts (or goes low), as the FIFO_DC is no lon-
ger empty. In this figure we assume that the Almost Empty setting flag setting is 3 (address location 3). So the
Almost Empty flag is de-asserted when the third address location is filled.
Now let us assume that we continue to write into the FIFO_DC to fill it. When the FIFO_DC is filled, the Almost Full
and Full Flags are asserted. Figure 11-31 shows the behavior of these flags. In this figure the FIFO_DC depth is
'N'.
RPReset
WrClock
RdClock
Almost
Almost
Empty
Empty
Reset
WrEn
RdEn
Data
Full
Full
Q
Invalid Data
Data_1
Data_2
11-29
Invalid Q
Data_3
LatticeECP2/M Memory Usage Guide
Data_4
Data_5