LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 711

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

Lattice Semiconductor
The host sends the preamble, BDB3 (hex), and then sends the read command. The LatticeECP2/M sends read
data on D[0:7], driving BUSY high as needed to pause data flow. For an example bitstream see Table 15-7.
Table 15-8 lists the various read commands. Note that the sample bitstream and the list of read commands are for
reference only; to help the user better understand the flow. The actual bitstream, containing the read commands, is
generated by ispLEVER or Diamond and ispVM, the host, toggles the control signals and sends the bitstream.
Table 15-7. Parallel Port Read Bitstream Example
Table 15-8. Parallel Port Read Commands
Slave Parallel mode can support two types of overflow, Bypass and Flowthrough. After the first device has received
all of it’s configuration data, and the Bypass command is detected in the bitstream, the data presented to the D[0:7]
pins will be serialized and bypassed to the DOUT pin (see Figure 15-9). If the Flowthrough command is detected in
the bitstream, instead of the bypass command, the CSON signal will drive the following parallel mode device’s chip
select low as shown in Figure 15-10. If either type of overflow is active, driving both the CSN and CS1N pins high
will reset overflow, i.e. take the device out of overflow.
Reset Address
Read Increment
Read Usercode
Read Ctrl Reg 0
Read CRC
Read ID Code
NO OP
Note: x = don't care, v = variable.
Command
Header
Verify ID
Reset Address
Read Increment
32-bit Opcode
Frame
E2000000
83000000
84000000
86000000
87000000
01vvvvvv
FF
Reset address register to point to the first data frame
Read back the configuration memory frame selected by the address register and
post increment the address
Read the content of the USERCODE register
Read the content of Control Register 0
Read CRC register content
Read ID code
No operation. This is an 8-bit Opcode. Extra bits should not be appended to this
Opcode as this could cause INITN to go low during configuration.
1111...1111
10111101
10110011
Contents
15-15
2 Dummy Bytes
2-byte Preamble (BDB3)
8 bytes of command and data
4 bytes of command and data
4 bytes of command and data
LatticeECP2/M sysCONFIG Usage Guide
Description
Function