LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 670

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

June 2010
Introduction
This technical note discusses how to access the features of the LatticeECP2™ and LatticeECP2M™ sysDSP™
(Digital Signal Processing) Block described in the
DSP Block can offer significant improvement over traditional LUT-based implementations. Table 14-1 provides an
example of the performance and area benefits of this approach:
Table 14-1. sysDSP Block vs. LUT-based Multipliers
sysDSP Block Hardware
The LatticeECP2/M sysDSP Blocks are located in rows throughout device. Below is a block diagram of one of the
sysDSP Blocks:
Figure 14-1. LatticeECP2/M sysDSP Block
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Input Registers from
SRO of left-side
sysDSP Block (or
tied to zero if none)
Intermediate
Pipeline Registers
1. These timing numbers were generated using the ispLEVER
Multiplier Width
version.
Output
Registers
18x18
36x36
9x9
*Can only be routed to general logic routing when configured with less than
three MULT18X18.
Note: Each sysDSP Block spans nine columns of PFUs.
36
Add/Sub (36) (9x9 ≤ 2x18) 1
9x9
PR0 (36)
Mult18-0
Input, Multiplier, Output
Input, Multiplier, Output
Input, Multiplier, Output
Accumulator (52) 1
In Reg A0
In Reg B0
Register Pipelining
9x9
Summation (38) (Two 20 Bits in 9x9 Mode)
9x9
PR1 (36)
Mult18-1
In Reg A1
In Reg B1
36x36 (Mult36)
9x9
LatticeECP2/M Family Data
f
In Reg A2
In Reg B2
Uses One sysDSP Block
MAX
9x9
Add/Sub (36) (9x9 ≤ 2x18) 3
14-1
PR2 (36)
Mult18-2
®
404
420
371
design tool. Exact performance may vary with design and tool
LatticeECP2-50-7
Accumulator (52) 3
(MHz)
9x9
1
In Reg A3
In Reg B3
LatticeECP2/M sysDSP
9x9
LUTs
PR3 (36)
Mult18-3
0
0
0
9x9
Sheet. Designs targeting the sys-
f
36
MAX
124
LatticeECP2-50-7
95
61
(MHz)
Uses LUTs
Usage Guide
Adder, Subtractor and
Accumulator Functions
36x36, 18x18 and
9x9 Multiplier Functions
Output Registers to SRI
of right-side sysDSP Block
(if it exists) and/or General
Logic*
1
Technical Note TN1107
LUTs
2732
192
698
tn1107_01.3