TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 123

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

Bit
5:4
2:0
6
3
Mnemonic
SHWT
RDY
ME
SP
Ready Input
Mode
Bus Speed
Master Enable
Set Up/Hold
Wait Time
Field Name
Figure 7.4.1 External Bus Channel Control Register (3/3)
External Bus Control Ready Input Mode (Default: 0)
Specifies whether to use the Ready mode.
0: Disable the Ready mode.
1: Enable the Ready mode.
Note: The Ready mode cannot be used when the Page mode is selected.
External Bus Control Bus Speed (Default: ADDR[7:6] / 00)
Specifies the External Bus speed.
00: 1/4 speed (1/4 of the GBUSCLK frequency)
01: 1/3 speed (1/3 of the GBUSCLK frequency)
10: 1/2 speed (1/2 of the GBUSCLK frequency)
11: Full speed (same frequency as GBUSCLK)
Note: ADDR[7:6] is set to Channel 0 as the default.
External Bus Control Master Enable (Default: ADDR[8] / 0)
Enables a channel.
0: Disable channel
1: Enable channel
Note: ADDR[8] is set to Channel 0 as the default.
External Bus Control Setup/Hold Wait Time (Default: 000)
Specifies the wait count when switching between the Address and Chip
Enable signal, or the Chip Enable Signal and Write Enable/Output Enable
signal.
* 000: Disable
* Set this bit field to “0” when using it in the Page mode or when performing
Burst access.
001: 1wait cycle
010: 2 wait cycles
011: 3 wait cycles
7-23
100: 4 wait cycles
101: 5 wait cycles
110: 6 wait cycles
111: 7 wait cycles
Chapter 7 External Bus Controller
Description
Read/Write
R/W
R/W
R/W
R/W